Browse Source

optimize code standard

crypto_algorithm
Liu_Weichao 1 year ago
parent
commit
adcfd5e7f6
  1. 14
      arch/arm/cortex-m4/kswitch.h
  2. 66
      board/aiit-arm32-board/third_party_driver/can/connect_can.c
  3. 172
      board/aiit-arm32-board/third_party_driver/ch438/connect_ch438.c
  4. 134
      board/aiit-arm32-board/third_party_driver/gpio/connect_gpio.c
  5. 38
      board/aiit-arm32-board/third_party_driver/i2c/connect_i2c.c
  6. 3
      board/aiit-arm32-board/third_party_driver/include/connect_can.h
  7. 170
      board/aiit-arm32-board/third_party_driver/include/connect_ch438.h
  8. 6
      board/aiit-arm32-board/third_party_driver/include/connect_spi.h
  9. 45
      board/aiit-arm32-board/third_party_driver/include/connect_touch.h
  10. 6
      board/aiit-arm32-board/third_party_driver/include/connect_usart.h
  11. 2
      board/aiit-arm32-board/third_party_driver/rtc/connect_rtc.c
  12. 73
      board/aiit-arm32-board/third_party_driver/sdio/connect_sdio.c
  13. 6
      board/aiit-arm32-board/third_party_driver/spi/connect_flash_spi.c
  14. 268
      board/aiit-arm32-board/third_party_driver/spi/connect_spi.c
  15. 27
      board/aiit-arm32-board/third_party_driver/timer/connect_hwtimer.c
  16. 214
      board/aiit-arm32-board/third_party_driver/touch/connect_touch.c
  17. 86
      board/aiit-arm32-board/third_party_driver/uart/connect_usart.c
  18. 13
      board/aiit-arm32-board/third_party_driver/usb/connect_usb.c
  19. 18
      board/aiit-arm32-board/third_party_driver/watchdog/connect_wdg.c
  20. 6
      board/aiit-riscv64-board/third_party_driver/ch376/connect_ch376.c
  21. 210
      board/aiit-riscv64-board/third_party_driver/ch438/connect_ch438.c
  22. 10
      board/aiit-riscv64-board/third_party_driver/i2c/connect_i2c.c
  23. 2
      board/aiit-riscv64-board/third_party_driver/include/connect_ch376.h
  24. 144
      board/aiit-riscv64-board/third_party_driver/include/connect_ch438.h
  25. 13
      board/aiit-riscv64-board/third_party_driver/include/connect_lcd.h
  26. 16
      board/aiit-riscv64-board/third_party_driver/include/connect_touch.h
  27. 4
      board/aiit-riscv64-board/third_party_driver/include/connect_uart.h
  28. 540
      board/aiit-riscv64-board/third_party_driver/lcd/connect_lcd.c
  29. 2
      board/aiit-riscv64-board/third_party_driver/rtc/connect_rtc.c
  30. 4
      board/aiit-riscv64-board/third_party_driver/timer/connect_hwtimer.c
  31. 42
      board/aiit-riscv64-board/third_party_driver/touch/connect_touch.c
  32. 63
      board/hifive1-emulator/third_party_driver/connect_usart.c
  33. 63
      board/hifive1-rev-B/third_party_driver/connect_usart.c
  34. 28
      board/kd233/third_party_driver/i2c/connect_i2c.c
  35. 4
      board/kd233/third_party_driver/include/connect_uart.h
  36. 6
      board/kd233/third_party_driver/spi/connect_spi.c
  37. 4
      board/kd233/third_party_driver/timer/connect_hwtimer.c
  38. 63
      board/stm32f407-st-discovery/third_party_driver/can/connect_can.c
  39. 65
      board/stm32f407-st-discovery/third_party_driver/gpio/connect_gpio.c
  40. 40
      board/stm32f407-st-discovery/third_party_driver/i2c/connect_i2c.c
  41. 1
      board/stm32f407-st-discovery/third_party_driver/include/connect_can.h
  42. 6
      board/stm32f407-st-discovery/third_party_driver/include/connect_spi.h
  43. 6
      board/stm32f407-st-discovery/third_party_driver/include/connect_usart.h
  44. 2
      board/stm32f407-st-discovery/third_party_driver/rtc/connect_rtc.c
  45. 48
      board/stm32f407-st-discovery/third_party_driver/sdio/connect_sdio.c
  46. 4
      board/stm32f407-st-discovery/third_party_driver/spi/connect_flash_spi.c
  47. 191
      board/stm32f407-st-discovery/third_party_driver/spi/connect_spi.c
  48. 29
      board/stm32f407-st-discovery/third_party_driver/timer/connect_hwtimer.c
  49. 95
      board/stm32f407-st-discovery/third_party_driver/uart/connect_usart.c
  50. 10
      board/stm32f407-st-discovery/third_party_driver/usb/connect_usb.c
  51. 26
      board/stm32f407-st-discovery/third_party_driver/watchdog/connect_wdg.c
  52. 6
      board/stm32f407zgt6/third_party_driver/include/connect_usart.h
  53. 109
      board/stm32f407zgt6/third_party_driver/uart/connect_usart.c
  54. 4
      kernel/include/xs_assign.h
  55. 5
      kernel/include/xs_delay.h
  56. 80
      kernel/include/xs_kdevice.h
  57. 2
      kernel/include/xs_ktask.h
  58. 6
      kernel/include/xs_service.h
  59. 26
      kernel/include/xs_spinlock.h
  60. 2
      kernel/kernel_service/xs_service.c
  61. 10
      kernel/kernel_test/test_gatherblock.c
  62. 2
      kernel/kernel_test/test_hwtimer.c
  63. 8
      kernel/kernel_test/test_i2c.c
  64. 4
      kernel/thread/ktask.c
  65. 12
      kernel/thread/lock.c
  66. 6
      kernel/thread/msgqueue.c
  67. 1
      resources/can/dev_can.c
  68. 2
      resources/include/dev_hwtimer.h
  69. 2
      resources/include/dev_i2c.h
  70. 6
      resources/spi/sd_card_spi/sd_spi.c

14
arch/arm/cortex-m4/kswitch.h

@ -210,7 +210,7 @@ static inline unsigned long KSwitch0(unsigned int knum)
{
uintptr_t param[1] = {0};
uint8_t num = 0;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch1(unsigned int knum, unsigned long arg1)
@ -218,7 +218,7 @@ static inline unsigned long KSwitch1(unsigned int knum, unsigned long arg1)
uintptr_t param[1] = {0};
uint8_t num = 1;
param[0] = arg1;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
@ -229,7 +229,7 @@ static inline unsigned long KSwitch2(unsigned int knum, unsigned long arg1,
uint8_t num = 2;
param[0] = arg1;
param[1] = arg2;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
@ -242,7 +242,7 @@ static inline unsigned long KSwitch3(unsigned int knum, unsigned long arg1,
param[1] = arg2;
param[2] = arg3;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch4(unsigned int knum, unsigned long arg1,
@ -255,7 +255,7 @@ static inline unsigned long KSwitch4(unsigned int knum, unsigned long arg1,
param[1] = arg2;
param[2] = arg3;
param[3] = arg4;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch5(unsigned int knum, unsigned long arg1,
@ -269,7 +269,7 @@ static inline unsigned long KSwitch5(unsigned int knum, unsigned long arg1,
param[2] = arg3;
param[3] = arg4;
param[4] = arg5;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
static inline unsigned long KSwitch6(unsigned int knum, unsigned long arg1,
@ -285,7 +285,7 @@ static inline unsigned long KSwitch6(unsigned int knum, unsigned long arg1,
param[3] = arg4;
param[4] = arg5;
param[5] = arg6;
(struct Kernel_Service*)SERVICETABLE[knum].fun(knum, param, num);
(struct KernelService*)SERVICETABLE[knum].fun(knum, param, num);
}
#endif

66
board/aiit-arm32-board/third_party_driver/can/connect_can.c

@ -33,15 +33,14 @@ Modification:
static struct CanSendConfigure can_send_deconfig =
{
.stdid = 0x12,
.exdid = 0x12,
.ide = 0 ,
.rtr = 0,
.data_lenth = 8
.stdid = 0x12,
.exdid = 0x12,
.ide = 0 ,
.rtr = 0,
.data_lenth = 8
};
static void CanGPIOInit(void)
static void CanGPIOInit(void)
{
CAN_FilterInitTypeDef can1_filter;
GPIO_InitTypeDef gpio_initstructure;
@ -63,14 +62,14 @@ static void CanGPIOInit(void)
static void Can1NvicConfig(void)
{
NVIC_InitTypeDef can_nvic_config;
can_nvic_config.NVIC_IRQChannel = CAN1_RX0_IRQn;
can_nvic_config.NVIC_IRQChannelPreemptionPriority = 2;
can_nvic_config.NVIC_IRQChannelSubPriority = 2;
can_nvic_config.NVIC_IRQChannelCmd = ENABLE;
CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
NVIC_Init(&can_nvic_config);
NVIC_InitTypeDef can_nvic_config;
can_nvic_config.NVIC_IRQChannel = CAN1_RX0_IRQn;
can_nvic_config.NVIC_IRQChannelPreemptionPriority = 2;
can_nvic_config.NVIC_IRQChannelSubPriority = 2;
can_nvic_config.NVIC_IRQChannelCmd = ENABLE;
CAN_ITConfig(CAN1, CAN_IT_FMP0, ENABLE);
NVIC_Init(&can_nvic_config);
}
static uint32 CanModeInit(void *drv, struct BusConfigureInfo *configure_info)
@ -129,18 +128,17 @@ static uint32 CanSendMsg(void * dev , struct BusBlockWriteParam *write_param )
tx_data.RTR = 0;
tx_data.DLC = write_param->size;
for(i = 0;i<tx_data.DLC;i++)
{
for(i = 0;i < tx_data.DLC;i ++) {
tx_data.Data[i] = data[i];
}
messege_box = CAN_Transmit(CAN1,&tx_data);
while(CAN_TransmitStatus(CAN1,messege_box)== CAN_TxStatus_Failed &&timer_count){
timer_count--;
while (CAN_TransmitStatus(CAN1,messege_box)== CAN_TxStatus_Failed &&timer_count) {
timer_count--;
}
if(timer_count<=0){
if (timer_count<=0) {
return ERROR;
}
return EOK;
@ -152,17 +150,16 @@ static uint32 CanRecvMsg(void *dev , struct BusBlockReadParam *databuf)
int i;
uint8 * buf = (uint8 *)databuf->buffer;
CanRxMsg msg;
if(CAN_MessagePending(CAN1, CAN_FIFO0) == 0)
if (CAN_MessagePending(CAN1, CAN_FIFO0) == 0)
return 0;
CAN_Receive(CAN1, CAN_FIFO0, &msg);
for(i = 0 ;i<msg.DLC ;i++)
for(i = 0 ;i < msg.DLC;i ++)
buf[i] = msg.Data[i];
databuf->size = msg.DLC ;
return msg.DLC;
}
static struct CanDevDone dev_done =
{
.open = NONE,
@ -171,43 +168,41 @@ static struct CanDevDone dev_done =
.read = CanRecvMsg
};
static struct CanHardwareDevice dev;
#ifdef CAN_USING_INTERRUPT
void CAN1_RX0_IRQHandler(void)
{
CanRxMsg rxmsg;
int i = 0;
CAN_Receive(CAN1, 0, &rxmsg);
for(i = 0;i<8;i++)
for (i = 0;i < 8;i ++)
KPrintf("rxbuf [%d] = :%d",i,rxmsg.Data[i]);
}
DECLARE_HW_IRQ(CAN1_RX0_IRQn, CAN1_RX0_IRQHandler, NONE);
#endif
static int BoardCanBusInit(struct Stm32Can *stm32can_bus, struct CanDriver *can_driver)
{
x_err_t ret = EOK;
/*Init the can bus */
ret = CanBusInit(&stm32can_bus->can_bus, stm32can_bus->bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_can_init canBusInit error %d\n", ret);
return ERROR;
}
/*Init the can driver*/
ret = CanDriverInit(can_driver, CAN_DRIVER_NAME);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_can_init canDriverInit error %d\n", ret);
return ERROR;
}
/*Attach the can driver to the can bus*/
ret = CanDriverAttachToBus(CAN_DRIVER_NAME, stm32can_bus->bus_name);
if(EOK != ret){
if (EOK != ret) {
KPrintf("Board_can_init CanDriverAttachToBus error %d\n", ret);
return ERROR;
}
@ -215,8 +210,6 @@ static int BoardCanBusInit(struct Stm32Can *stm32can_bus, struct CanDriver *can_
return ret;
}
static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
{
NULL_PARAM_CHECK(bus_name);
@ -232,13 +225,13 @@ static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
can_device->dev_done = &dev_done;
result = CanDeviceRegister(can_device, NONE, device_name);
if(EOK != result){
if (EOK != result) {
KPrintf("board_can_init canDeviceInit device %s error %d\n", "can1", result);
return ERROR;
}
result = CanDeviceAttachToBus(device_name, bus_name);
if (result != EOK){
if (result != EOK) {
SYS_ERR("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
@ -249,7 +242,6 @@ static x_err_t HwCanDeviceAttach(const char *bus_name, const char *device_name)
return result;
}
struct Stm32Can can1;
int Stm32HwCanBusInit(void)
@ -269,13 +261,13 @@ struct Stm32Can can1;
ret = BoardCanBusInit(stm32_can_bus, &can_driver);
if(EOK != ret){
if (EOK != ret) {
KPrintf(" can_bus_init %s error ret %u\n", stm32_can_bus->bus_name, ret);
return ERROR;
}
ret = HwCanDeviceAttach(CAN_BUS_NAME_1,CAN_1_DEVICE_NAME_1);
if(EOK != ret) {
if (EOK != ret) {
KPrintf(" HwCanDeviceAttach %s error ret %u\n", stm32_can_bus->bus_name, ret);
return ERROR;
}

172
board/aiit-arm32-board/third_party_driver/ch438/connect_ch438.c

@ -20,14 +20,14 @@
#include <connect_ch438.h>
static const uint8 offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* uart offset address*/
static const uint8 Interruptnum[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,}; /* SSR register data*/
static const uint8 offset_addr[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* uart offset address*/
static const uint8 interrupt_num[8] = {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,}; /* SSR register data*/
static BusType ch438_pin;
static int Ch438Sem = NONE;
static int ch438_sem = NONE;
static void Ch438Irq(void *parameter)
{
KSemaphoreAbandon(Ch438Sem);
KSemaphoreAbandon(ch438_sem);
}
/**
@ -43,8 +43,7 @@ static void Stm32Udelay(uint32 us)
ticks = us * reload / (1000000 / TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
while (1) {
tnow = SysTick->VAL;
if (tnow != told) {
if (tnow < told) {
@ -612,14 +611,13 @@ void WriteCH438Data(uint8 addr, uint8 dat)
********************************************************************************************************/
void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf)
{
while (mlen--)
{
while (mlen--) {
WriteCH438Data(maddr, *mbuf++);
}
}
/*********************************************************************************************************
** Function name: CH438UartSend
** Function name: Ch438UartSend
** Function: active FIFO mode, CH438 send multibyte data by uart 0, max length is 128 bytes a single time
** input: send data cache address, send data length
**
@ -631,15 +629,14 @@ void WriteCH438Block(uint8 maddr, uint8 mlen, uint8 *mbuf)
** date:
**-------------------------------------------------------------------------------------------------------
********************************************************************************************************/
void CH438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num )
void Ch438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num )
{
uint8 REG_LSR_ADDR,REG_THR_ADDR;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
while (1)
{
while (1) {
while((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_TEMT) == 0); /* wait for sending data done, THR and TSR is NULL */
if (Num <= 128) {
@ -654,7 +651,7 @@ void CH438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num )
}
/*********************************************************************************************************
** Function name: CH438UARTRcv
** Function name: Ch438UartRcv
** Function: forbidden FIFO mode, CH438 receive multibyte data from uart 0
** input: recv data address
**
@ -666,7 +663,7 @@ void CH438UartSend( uint8 ext_uart_no,uint8 *data, uint8 Num )
** date:
**-------------------------------------------------------------------------------------------------------
********************************************************************************************************/
uint8 CH438UARTRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size)
uint8 Ch438UartRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size)
{
uint8 rcv_num = 0;
uint8 dat = 0;
@ -676,13 +673,12 @@ uint8 CH438UARTRcv(uint8 ext_uart_no, uint8 *buf, x_size_t size)
read_buffer = buf;
REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_LSR_ADDR = offset_addr[ext_uart_no] | REG_LSR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
while ((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0); /* wait for data is ready */
while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0))
{
while (((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) && (size != 0)) {
dat = ReadCH438Data(REG_RBR_ADDR);
*read_buffer = dat;
@ -705,50 +701,42 @@ static void Timeout438Proc(void *parameter)
{
uint8_t rbr,lsr;
while( ( ReadCH438Data( REG_LSR0_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR0_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR0_ADDR );
KPrintf("0.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR1_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR1_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR1_ADDR );
KPrintf("1.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR2_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR2_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR2_ADDR );
KPrintf("2.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR3_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR3_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR3_ADDR );
KPrintf("3.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR4_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR4_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR4_ADDR );
KPrintf("4.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR5_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR5_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR5_ADDR );
KPrintf("5.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR6_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR6_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR6_ADDR );
KPrintf("6.RBR=%02x\r\n",rbr);
}
while( ( ReadCH438Data( REG_LSR7_ADDR ) & BIT_LSR_DATARDY ) == 0x01 )
{
while( ( ReadCH438Data( REG_LSR7_ADDR ) & BIT_LSR_DATARDY ) == 0x01 ) {
rbr = ReadCH438Data( REG_RBR7_ADDR );
KPrintf("7.RBR=%02x\r\n",rbr);
}
@ -804,7 +792,7 @@ void Set485Output(uint8 ch_no)
}
}
void CH438_PORT_INIT( uint8 ext_uart_no,uint32 BaudRate )
void Ch438PortInit( uint8 ext_uart_no,uint32 BaudRate )
{
uint32 div;
uint8 DLL,DLM,dlab;
@ -818,15 +806,15 @@ void CH438_PORT_INIT( uint8 ext_uart_no,uint32 BaudRate )
uint8 REG_THR_ADDR;
uint8 REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */
MdelayKTask(50);
@ -869,15 +857,15 @@ void CH438PortInitParityCheck(uint8 ext_uart_no, uint32 BaudRate)
uint8 REG_THR_ADDR;
uint8 REG_IIR_ADDR;
REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR;
REG_LCR_ADDR = offset_addr[ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[ext_uart_no] | REG_IIR0_ADDR;
WriteCH438Data(REG_IER_ADDR, BIT_IER_RESET); /* reset the uart */
MdelayKTask(50);
@ -913,7 +901,7 @@ static uint32 Stm32Ch438Configure(struct SerialCfgParam *ext_serial_cfg)
switch (ext_serial_cfg->data_cfg.port_configure)
{
case PORT_CFG_INIT:
CH438_PORT_INIT(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
Ch438PortInit(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
break;
case PORT_CFG_PARITY_CHECK:
CH438PortInitParityCheck(ext_serial_cfg->data_cfg.ext_uart_no, ext_serial_cfg->data_cfg.serial_baud_rate);
@ -1040,11 +1028,11 @@ static uint32 Stm32Ch438DrvConfigure(void *drv, struct BusConfigureInfo *configu
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32Ch438Init(serial_drv, ext_serial_cfg);
break;
default:
break;
case OPE_INT:
ret = Stm32Ch438Init(serial_drv, ext_serial_cfg);
break;
default:
break;
}
return ret;
@ -1058,7 +1046,7 @@ static uint32 Stm32Ch438WriteData(void *dev, struct BusBlockWriteParam *write_pa
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
CH438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size);
Ch438UartSend(dev_param->ext_uart_no, (uint8 *)write_param->buffer, write_param->size);
return EOK;
}
@ -1088,7 +1076,7 @@ static uint32 Stm32Ch438ReadData(void *dev, struct BusBlockReadParam *read_param
struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
struct SerialDevParam *dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
result = KSemaphoreObtain(Ch438Sem, WAITING_FOREVER);
result = KSemaphoreObtain(ch438_sem, WAITING_FOREVER);
if (EOK == result) {
gInterruptStatus = ReadCH438Data(REG_SSR_ADDR);
if (!gInterruptStatus) {
@ -1102,18 +1090,18 @@ static uint32 Stm32Ch438ReadData(void *dev, struct BusBlockReadParam *read_param
dat = ReadCH438Data(REG_IIR0_ADDR);
dat = dat ;
} else {
if (gInterruptStatus & Interruptnum[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/
REG_LCR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offsetadd[dev_param->ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offsetadd[dev_param->ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offsetadd[dev_param->ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_IIR0_ADDR;
REG_LSR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_LSR0_ADDR;
REG_MSR_ADDR = offsetadd[dev_param->ext_uart_no] | REG_MSR0_ADDR;
if (gInterruptStatus & interrupt_num[dev_param->ext_uart_no]) { /* check which uart port triggers interrupt*/
REG_LCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LCR0_ADDR;
REG_DLL_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLL0_ADDR;
REG_DLM_ADDR = offset_addr[dev_param->ext_uart_no] | REG_DLM0_ADDR;
REG_IER_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IER0_ADDR;
REG_MCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MCR0_ADDR;
REG_FCR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_FCR0_ADDR;
REG_RBR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_RBR0_ADDR;
REG_THR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_THR0_ADDR;
REG_IIR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_IIR0_ADDR;
REG_LSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_LSR0_ADDR;
REG_MSR_ADDR = offset_addr[dev_param->ext_uart_no] | REG_MSR0_ADDR;
InterruptStatus = ReadCH438Data( REG_IIR_ADDR ) & 0x0f; /* read the status of the uart port*/
@ -1125,7 +1113,7 @@ static uint32 Stm32Ch438ReadData(void *dev, struct BusBlockReadParam *read_param
break;
case INT_RCV_OVERTIME: /* RECV OVERTIME INTERRUPT*/
case INT_RCV_SUCCESS: /* RECV INTERRUPT SUCCESSFULLY*/
rcv_num = CH438UARTRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size);
rcv_num = Ch438UartRcv(dev_param->ext_uart_no, (uint8 *)read_param->buffer, read_param->size);
read_param->read_length = rcv_num;
break;
case INT_RCV_LINES: /* RECV LINES INTERRUPT */
@ -1162,8 +1150,8 @@ static void Stm32Ch438InitDefault(struct SerialDriver *serial_drv)
configure_info.configure_cmd = OPE_CFG;
configure_info.private_data = (void *)&PinCfg;
Ch438Sem = KSemaphoreCreate(0);
if (Ch438Sem < 0) {
ch438_sem = KSemaphoreCreate(0);
if (ch438_sem < 0) {
KPrintf("Ch438InitDefault create sem failed .\n");
return ;
}
@ -1375,21 +1363,21 @@ void CH438RegTest(unsigned char num)//for test
{
uint8 dat;
KPrintf("current test serilnum: %02x \r\n",offsetadd[num]);
KPrintf("IER: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_IER0_ADDR));//?IER
KPrintf("IIR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_IIR0_ADDR));//?IIR
KPrintf("LCR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_LCR0_ADDR));//?LCR
KPrintf("MCR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_MCR0_ADDR));//?MCR
KPrintf("LSR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_LSR0_ADDR));//?LSR
KPrintf("MSR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_MSR0_ADDR));//?MSR
KPrintf("FCR: %02x\r\n",ReadCH438Data(offsetadd[num] | REG_FCR0_ADDR));//?FCR
KPrintf("SSR: %02x\r\n",ReadCH438Data( offsetadd[num] | REG_SSR_ADDR ));//?SSR
KPrintf("current test serilnum: %02x \r\n",offset_addr[num]);
KPrintf("IER: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IER0_ADDR));//?IER
KPrintf("IIR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_IIR0_ADDR));//?IIR
KPrintf("LCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LCR0_ADDR));//?LCR
KPrintf("MCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MCR0_ADDR));//?MCR
KPrintf("LSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_LSR0_ADDR));//?LSR
KPrintf("MSR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_MSR0_ADDR));//?MSR
KPrintf("FCR: %02x\r\n",ReadCH438Data(offset_addr[num] | REG_FCR0_ADDR));//?FCR
KPrintf("SSR: %02x\r\n",ReadCH438Data( offset_addr[num] | REG_SSR_ADDR ));//?SSR
KPrintf("SCR0: %02x\r\n",(unsigned short)ReadCH438Data(offsetadd[num] | REG_SCR0_ADDR));//?SCR
KPrintf("SCR0: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
dat = 0x55;
WriteCH438Data(offsetadd[num] | REG_SCR0_ADDR, dat);
KPrintf("SCR55: %02x\r\n",(unsigned short)ReadCH438Data(offsetadd[num] | REG_SCR0_ADDR));//?SCR
WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat);
KPrintf("SCR55: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
dat = 0xAA;
WriteCH438Data(offsetadd[num] | REG_SCR0_ADDR, dat);
KPrintf("SCRAA: %02x\r\n",(unsigned short)ReadCH438Data(offsetadd[num] | REG_SCR0_ADDR));//?SCR
WriteCH438Data(offset_addr[num] | REG_SCR0_ADDR, dat);
KPrintf("SCRAA: %02x\r\n",(unsigned short)ReadCH438Data(offset_addr[num] | REG_SCR0_ADDR));//?SCR
}

134
board/aiit-arm32-board/third_party_driver/gpio/connect_gpio.c

@ -55,7 +55,7 @@ struct PinIrq
{
uint8 port_source;
uint8 pin_source;
enum IRQn irq_exti_Channel;
enum IRQn irq_exti_channel;
uint32 exti_line;
};
@ -510,8 +510,7 @@ static int32 GpioConfigMode(int mode, const struct PinIndex* index)
static __inline int32 Bit2Bitnum(uint32 bit)
{
for (int i = 0; i < 32; i++)
{
for (int i = 0; i < 32; i++) {
if ((1UL << i) == bit) {
return i;
}
@ -521,10 +520,9 @@ static __inline int32 Bit2Bitnum(uint32 bit)
static __inline int32 Bitno2Bit(uint32 bitno)
{
if (bitno <= 32){
if (bitno <= 32) {
return 1UL << bitno;
}
else{
} else {
return 0;
}
}
@ -533,7 +531,7 @@ static const struct PinIrq *GetPinIrq(uint16_t pin)
static struct PinIrq irq;
const struct PinIndex* index = GetPin(pin);
if (index == NONE){
if (index == NONE) {
return NONE;
}
@ -542,35 +540,35 @@ static const struct PinIrq *GetPinIrq(uint16_t pin)
irq.port_source = ((uint32_t)index->gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE);
switch (irq.pin_source)
{
case 0 : irq.irq_exti_Channel = EXTI0_IRQn;break;
case 1 : irq.irq_exti_Channel = EXTI1_IRQn;break;
case 2 : irq.irq_exti_Channel = EXTI2_IRQn;break;
case 3 : irq.irq_exti_Channel = EXTI3_IRQn;break;
case 4 : irq.irq_exti_Channel = EXTI4_IRQn;break;
case 5 :
case 6 :
case 7 :
case 8 :
case 9 : irq.irq_exti_Channel = EXTI9_5_IRQn;break;
case 10 :
case 11 :
case 12 :
case 13 :
case 14 :
case 15 : irq.irq_exti_Channel = EXTI15_10_IRQn;break;
default : return NONE;
case 0 : irq.irq_exti_channel = EXTI0_IRQn;break;
case 1 : irq.irq_exti_channel = EXTI1_IRQn;break;
case 2 : irq.irq_exti_channel = EXTI2_IRQn;break;
case 3 : irq.irq_exti_channel = EXTI3_IRQn;break;
case 4 : irq.irq_exti_channel = EXTI4_IRQn;break;
case 5 :
case 6 :
case 7 :
case 8 :
case 9 : irq.irq_exti_channel = EXTI9_5_IRQn;break;
case 10 :
case 11 :
case 12 :
case 13 :
case 14 :
case 15 : irq.irq_exti_channel = EXTI15_10_IRQn;break;
default : return NONE;
}
return &irq;
};
static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), void *args)
{
const struct PinIndex* index = GetPin(pin);
int32 irqindex = -1;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab))
{
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
}
@ -584,7 +582,7 @@ static int32 GpioIrqRegister(int32 pin, int32 mode, void (*hdr)(void *args), voi
CriticalAreaUnLock(level);
return EOK;
}
if (pin_irq_hdr_tab[irqindex].pin != -1){
if (pin_irq_hdr_tab[irqindex].pin != -1) {
CriticalAreaUnLock(level);
return -EDEV_BUSY;
}
@ -603,7 +601,7 @@ static uint32 GpioIrqFree(int32 pin)
int32 irqindex = -1;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return ENONESYS;
}
@ -630,17 +628,17 @@ static int32 GpioIrqEnable(x_base pin)
EXTI_InitTypeDef exit_init_structure;
irqindex = Bit2Bitnum(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)){
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) {
return -ENONESYS;
}
x_base level = CriticalAreaLock();
if (pin_irq_hdr_tab[irqindex].pin == -1){
if (pin_irq_hdr_tab[irqindex].pin == -1) {
CriticalAreaUnLock(level);
return -ENONESYS;
}
irq = GetPinIrq(pin);
if (irq == NONE){
if (irq == NONE) {
CriticalAreaUnLock(level);
return -ENONESYS;
}
@ -649,19 +647,19 @@ static int32 GpioIrqEnable(x_base pin)
exit_init_structure.EXTI_Mode = EXTI_Mode_Interrupt;
switch (pin_irq_hdr_tab[irqindex].mode)
{
case GPIO_IRQ_EDGE_RISING:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising;
break;
case GPIO_IRQ_EDGE_FALLING:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case GPIO_IRQ_EDGE_BOTH:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
case GPIO_IRQ_EDGE_RISING:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising;
break;
case GPIO_IRQ_EDGE_FALLING:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case GPIO_IRQ_EDGE_BOTH:
exit_init_structure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
}
exit_init_structure.EXTI_LineCmd = ENABLE;
EXTI_Init(&exit_init_structure);
NVIC_InitStructure.NVIC_IRQChannel = irq->irq_exti_Channel;
NVIC_InitStructure.NVIC_IRQChannel = irq->irq_exti_channel;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
@ -724,7 +722,7 @@ static uint32 Stm32PinInit(void)
{
static x_bool PinInitFlag = RET_FALSE;
if(!PinInitFlag) {
if (!PinInitFlag) {
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
PinInitFlag = RET_TRUE;
}
@ -742,15 +740,15 @@ static uint32 Stm32GpioDrvConfigure(void *drv, struct BusConfigureInfo *configur
switch (configure_info->configure_cmd)
{
case OPE_INT:
ret = Stm32PinInit();
break;
case OPE_CFG:
param = (struct PinParam *)configure_info->private_data;
ret = Stm32PinConfigure(param);
break;
default:
break;
case OPE_INT:
ret = Stm32PinInit();
break;
case OPE_CFG:
param = (struct PinParam *)configure_info->private_data;
ret = Stm32PinConfigure(param);
break;
default:
break;
}
return ret;
@ -764,10 +762,9 @@ uint32 Stm32PinWrite(void *dev, struct BusBlockWriteParam *write_param)
const struct PinIndex* index = GetPin(pinstat->pin);
NULL_PARAM_CHECK(index);
if (GPIO_LOW == pinstat->val){
if (GPIO_LOW == pinstat->val) {
GPIO_ResetBits(index->gpio, index->pin);
}
else{
} else {
GPIO_SetBits(index->gpio, index->pin);
}
return EOK;
@ -781,7 +778,7 @@ uint32 Stm32PinRead(void *dev, struct BusBlockReadParam *read_param)
const struct PinIndex* index = GetPin(pinstat->pin);
NULL_PARAM_CHECK(index);
if(GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) {
if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) {
pinstat->val = GPIO_LOW;
} else {
pinstat->val = GPIO_HIGH;
@ -804,7 +801,7 @@ int Stm32HwGpioInit(void)
static struct PinBus pin;
ret = PinBusInit(&pin, PIN_BUS_NAME);
if(ret != EOK){
if (ret != EOK) {
KPrintf("gpio bus init error %d\n", ret);
return ERROR;
}
@ -813,12 +810,12 @@ int Stm32HwGpioInit(void)
drv.configure = &Stm32GpioDrvConfigure;
ret = PinDriverInit(&drv, PIN_DRIVER_NAME, NONE);
if(ret != EOK){
if (ret != EOK) {
KPrintf("pin driver init error %d\n", ret);
return ERROR;
}
ret = PinDriverAttachToBus(PIN_DRIVER_NAME, PIN_BUS_NAME);
if(ret != EOK) {
if (ret != EOK) {
KPrintf("pin driver attach error %d\n", ret);
return ERROR;
}
@ -827,12 +824,12 @@ int Stm32HwGpioInit(void)
dev.dev_done = &dev_done;
ret = PinDeviceRegister(&dev, NONE, PIN_DEVICE_NAME);
if(ret != EOK) {
if (ret != EOK) {
KPrintf("pin device register error %d\n", ret);
return ERROR;
}
ret = PinDeviceAttachToBus(PIN_DEVICE_NAME, PIN_BUS_NAME);
if(ret != EOK) {
if (ret != EOK) {
KPrintf("pin device register error %d\n", ret);
return ERROR;
}
@ -843,8 +840,7 @@ int Stm32HwGpioInit(void)
static __inline void PinIrqHdr(int irqno)
{
EXTI_ClearITPendingBit(Bitno2Bit(irqno));
if (pin_irq_hdr_tab[irqno].hdr)
{
if (pin_irq_hdr_tab[irqno].hdr) {
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
}
}
@ -881,19 +877,19 @@ DECLARE_HW_IRQ(EXTI4_IRQn, EXTI4_IRQHandler, NONE);
void EXTI9_5_IRQHandler(int irq_num, void *arg)
{
if (EXTI_GetITStatus(EXTI_Line5) != RESET){
if (EXTI_GetITStatus(EXTI_Line5) != RESET) {
PinIrqHdr(5);
}
if (EXTI_GetITStatus(EXTI_Line6) != RESET){
if (EXTI_GetITStatus(EXTI_Line6) != RESET) {
PinIrqHdr(6);
}
if (EXTI_GetITStatus(EXTI_Line7) != RESET){
if (EXTI_GetITStatus(EXTI_Line7) != RESET) {
PinIrqHdr(7);
}
if (EXTI_GetITStatus(EXTI_Line8) != RESET){
if (EXTI_GetITStatus(EXTI_Line8) != RESET) {
PinIrqHdr(8);
}
if (EXTI_GetITStatus(EXTI_Line9) != RESET){
if (EXTI_GetITStatus(EXTI_Line9) != RESET) {
PinIrqHdr(9);
}
}
@ -907,10 +903,10 @@ void EXTI15_10_IRQHandler(int irq_num, void *arg)
if (EXTI_GetITStatus(EXTI_Line11) != RESET) {
PinIrqHdr(11);
}
if (EXTI_GetITStatus(EXTI_Line12) != RESET){
if (EXTI_GetITStatus(EXTI_Line12) != RESET) {
PinIrqHdr(12);
}
if (EXTI_GetITStatus(EXTI_Line13) != RESET){
if (EXTI_GetITStatus(EXTI_Line13) != RESET) {
PinIrqHdr(13);
}
if (EXTI_GetITStatus(EXTI_Line14) != RESET) {

38
board/aiit-arm32-board/third_party_driver/i2c/connect_i2c.c

@ -49,11 +49,11 @@ static BusType pin;
#define SET_SDA(done, val) done->SetSdaState(done->data, val)
#define SET_SCL(done, val) done->SetSclState(done->data, val)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define SdaHigh(done) SET_SDA(done, 1)
#define SclLow(done) SET_SCL(done, 0)
#define GET_SDA(done) done->GetSdaState(done->data)
#define GET_SCL(done) done->GetSclState(done->data)
#define SdaLow(done) SET_SDA(done, 0)
#define SdaHigh(done) SET_SDA(done, 1)
#define SclLow(done) SET_SCL(done, 0)
static void I2cGpioInit(const I2cBusParam *bus_param)
{
@ -117,7 +117,6 @@ static void I2cGpioInit(const I2cBusParam *bus_param)
i2c_sda_stat.val = GPIO_HIGH;
write_param.buffer = (void *)&i2c_sda_stat;
BusDevWriteData(pin->owner_haldev, &write_param);
}
static void SetSdaState(void *data, uint8 sda_state)
@ -192,8 +191,7 @@ static uint8 GetSclState(void *data)
ticks = us * reload / (1000000 / TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
while (1) {
tnow = SysTick->VAL;
if (tnow != told) {
if (tnow < told) {
@ -227,8 +225,7 @@ static x_err_t I2cBusReset(const I2cBusParam *bus_param)
int32 i = 0;
if (GPIO_LOW == GetSdaState((void *)bus_param)) {
while (i++ < 9)
{
while (i++ < 9) {
SetSclState((void *)bus_param,GPIO_HIGH);
Stm32Udelay(100);
SetSclState((void *)bus_param,GPIO_LOW);
@ -258,13 +255,12 @@ static x_err_t SclHigh(struct I2cHalDrvDone *done)
SET_SCL(done, 1);
if(!done->GetSclState)
if (!done->GetSclState)
goto done;
start = CurrentTicksGain();
while (!GET_SCL(done))
{
if((CurrentTicksGain() - start) > done->timeout)
while (!GET_SCL(done)) {
if ((CurrentTicksGain() - start) > done->timeout)
return -ETIMEOUT;
DelayKTask((done->timeout + 1) >> 1);
}
@ -310,7 +306,7 @@ static __inline x_bool I2cWaitack(struct I2cHalDrvDone *done)
GET_SDA(done);
I2cDelay(done);
if(SclHigh(done) < 0) {
if (SclHigh(done) < 0) {
KPrintf("wait ack timeout");
return -ETIMEOUT;
}
@ -384,8 +380,7 @@ static x_size_t I2cSendBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
int32 count = msg->len;
uint16 ignore_nack = msg->flags & I2C_IGNORE_NACK;
while (count > 0)
{
while (count > 0) {
ret = I2cWriteb(bus, *ptr);
if ((ret > 0) || (ignore_nack && (ret == 0))) {
@ -431,8 +426,7 @@ static x_size_t I2cRecvBytes(struct I2cBus *bus, struct I2cDataStandard *msg)
int32 count = msg->len;
const uint32 flags = msg->flags;
while (count > 0)
{
while (count > 0) {
val = I2cReadb(bus);
if (val >= 0) {
*ptr = val;
@ -536,8 +530,7 @@ static uint32 I2cWriteData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStan
uint16 ignore_nack;
I2cStart(done);
while (NONE != msg)
{
while (NONE != msg) {
ignore_nack = msg->flags & I2C_IGNORE_NACK;
if (!(msg->flags & I2C_NO_START)) {
if (i) {
@ -579,8 +572,7 @@ static uint32 I2cReadData(struct I2cHardwareDevice *i2c_dev, struct I2cDataStand
uint16 ignore_nack;
I2cStart(done);
while (NONE != msg)
{
while (NONE != msg) {
ignore_nack = msg->flags & I2C_IGNORE_NACK;
if (!(msg->flags & I2C_NO_START)) {
if (i) {

3
board/aiit-arm32-board/third_party_driver/include/connect_can.h

@ -32,13 +32,10 @@ struct Stm32Can
CAN_InitTypeDef init;
uint8 can_flag;
struct CanBus can_bus;
};
int Stm32HwCanBusInit(void);
#endif

170
board/aiit-arm32-board/third_party_driver/include/connect_ch438.h

@ -33,47 +33,47 @@
#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */
#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */
#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */
#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */
#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */
#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */
#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port1 register address */
#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */
#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */
#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */
#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */
#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */
#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */
#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */
#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port2 register address */
#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */
#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */
#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */
#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */
#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */
#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */
#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */
#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */
@ -81,32 +81,32 @@
#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */
#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */
#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */
#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */
#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */
#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */
#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */
#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port4 register address */
#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */
#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */
#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */
#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */
#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */
#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */
#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */
#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */
@ -114,48 +114,48 @@
#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */
#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */
#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */
#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */
#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */
#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */
#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */
#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port6 register address */
#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */
#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */
#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */
#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */
#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */
#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */
#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */
#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */
/* CH438serial port7 register address */
#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */
#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */
#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */
#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */
#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */
#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */
#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */
#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */
#define REG_SSR_ADDR 0x4F /* pecial status register address */
@ -163,14 +163,14 @@
/* IER register bit */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */
#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */
#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */
#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */
#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */
#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */
#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */
/* IIR register bit */
@ -182,7 +182,7 @@
#define BIT_IIR_IID3 0x08
#define BIT_IIR_IID2 0x04
#define BIT_IIR_IID1 0x02
#define BIT_IIR_NOINT 0x01
#define BIT_IIR_NOINT 0x01
/* FCR register bit */
@ -192,18 +192,18 @@
#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */
/* LCR register bit */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */
#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/
/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */
#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */
#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */
#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */
/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */
@ -212,42 +212,42 @@
/* MCR register bit */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */
#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */
#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */
#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */
#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */
/* LSR register bit */
#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */
#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/
#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/
#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */
#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */