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And ok1052(cortex m7) board support from Huang_Yuqing

it is perfect
pull/3/head
xuedongliang 1 year ago
parent
commit
c079c8f80a
  1. 2
      Makefile
  2. 4
      arch/arm/Makefile
  3. 3
      arch/arm/cortex-m7/Makefile
  4. 29
      arch/arm/cortex-m7/arch_interrupt.h
  5. 148
      arch/arm/cortex-m7/boot.S
  6. 83
      arch/arm/cortex-m7/interrupt.c
  7. 308
      arch/arm/cortex-m7/interrupt_vector.S
  8. 52
      board/ok1052-c/Kconfig
  9. 5
      board/ok1052-c/Makefile
  10. 164
      board/ok1052-c/README.md
  11. 184
      board/ok1052-c/board.c
  12. 52
      board/ok1052-c/board.h
  13. 479
      board/ok1052-c/clock_config.c
  14. 81
      board/ok1052-c/clock_config.h
  15. 14
      board/ok1052-c/config.mk
  16. BIN
      board/ok1052-c/img/NXPBootUtility_1.png
  17. BIN
      board/ok1052-c/img/NXPBootUtility_2.png
  18. BIN
      board/ok1052-c/img/menuconfig.png
  19. BIN
      board/ok1052-c/img/menuconfig1.png
  20. BIN
      board/ok1052-c/img/terminal.png
  21. BIN
      board/ok1052-c/img/vscode.jpg
  22. 250
      board/ok1052-c/link.lds
  23. 81
      board/ok1052-c/pin_mux.c
  24. 86
      board/ok1052-c/pin_mux.h
  25. 266
      board/ok1052-c/third_party_driver/CMSIS/Include/cmsis_compiler.h
  26. 2088
      board/ok1052-c/third_party_driver/CMSIS/Include/cmsis_gcc.h
  27. 39
      board/ok1052-c/third_party_driver/CMSIS/Include/cmsis_version.h
  28. 2660
      board/ok1052-c/third_party_driver/CMSIS/Include/core_cm7.h
  29. 197
      board/ok1052-c/third_party_driver/CMSIS/Include/mpu_armv7.h
  30. 201
      board/ok1052-c/third_party_driver/CMSIS/LICENSE.txt
  31. 7
      board/ok1052-c/third_party_driver/Kconfig
  32. 42538
      board/ok1052-c/third_party_driver/MIMXRT1052/MIMXRT1052.h
  33. 625
      board/ok1052-c/third_party_driver/MIMXRT1052/MIMXRT1052_features.h
  34. 6
      board/ok1052-c/third_party_driver/MIMXRT1052/Makefile
  35. 5
      board/ok1052-c/third_party_driver/MIMXRT1052/drivers/Makefile
  36. 1211
      board/ok1052-c/third_party_driver/MIMXRT1052/drivers/fsl_clock.c
  37. 1471
      board/ok1052-c/third_party_driver/MIMXRT1052/drivers/fsl_clock.h
  38. 147
      board/ok1052-c/third_party_driver/MIMXRT1052/drivers/fsl_common.c
  39. 585
      board/ok1052-c/third_party_driver/MIMXRT1052/drivers/fsl_common.h
  40. 342
      board/ok1052-c/third_party_driver/MIMXRT1052/drivers/fsl_gpio.h
  41. 1240
      board/ok1052-c/third_party_driver/MIMXRT1052/drivers/fsl_iomuxc.h
  42. 2085
      board/ok1052-c/third_party_driver/MIMXRT1052/drivers/fsl_lpuart.c
  43. 855
      board/ok1052-c/third_party_driver/MIMXRT1052/drivers/fsl_lpuart.h
  44. 36
      board/ok1052-c/third_party_driver/MIMXRT1052/fsl_device_registers.h
  45. 235
      board/ok1052-c/third_party_driver/MIMXRT1052/system_MIMXRT1052.c
  46. 127
      board/ok1052-c/third_party_driver/MIMXRT1052/system_MIMXRT1052.h
  47. 7
      board/ok1052-c/third_party_driver/Makefile
  48. 42
      board/ok1052-c/third_party_driver/include/connect_uart.h
  49. 29
      board/ok1052-c/third_party_driver/uart/Kconfig
  50. 3
      board/ok1052-c/third_party_driver/uart/Makefile
  51. 409
      board/ok1052-c/third_party_driver/uart/connect_uart.c
  52. 12
      path_kernel.mk

2
Makefile

@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
.PHONY:COMPILE_APP COMPILE_KERNEL
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator ok1052-c
SRC_DIR:=
export BOARD ?=kd233

4
arch/arm/Makefile

@ -9,4 +9,8 @@ ifeq ($(CONFIG_BOARD_STM32F407_EVB),y)
SRC_DIR +=cortex-m4
endif
ifeq ($(CONFIG_BOARD_CORTEX_M7_EVB),y)
SRC_DIR +=cortex-m7
endif
include $(KERNEL_ROOT)/compiler.mk

3
arch/arm/cortex-m7/Makefile

@ -0,0 +1,3 @@
SRC_FILES := boot.S interrupt.c interrupt_vector.S
include $(KERNEL_ROOT)/compiler.mk

29
arch/arm/cortex-m7/arch_interrupt.h

@ -0,0 +1,29 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#ifndef ARCH_INTERRUPT_H__
#define ARCH_INTERRUPT_H__
#include <xs_base.h>
#define ARCH_MAX_IRQ_NUM (256)
#define ARCH_IRQ_NUM_OFFSET 0
#define SYSTICK_IRQN 15
#define UART1_IRQn 36
#define UART2_IRQn 37
int32 ArchEnableHwIrq(uint32 irq_num);
int32 ArchDisableHwIrq(uint32 irq_num);
#endif

148
arch/arm/cortex-m7/boot.S

@ -0,0 +1,148 @@
/* ------------------------------------------------------------------------- */
/* @file: startup_MIMXRT1052.s */
/* @purpose: CMSIS Cortex-M7 Core Device Startup File */
/* MIMXRT1052 */
/* @version: 1.0 */
/* @date: 2018-9-21 */
/* @build: b180921 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
/**
* @file boot.S
* @brief Contex-M7 start function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
/*************************************************
File name: boot.S
Description: Contex-M7 start function function
Others: take startup_MIMXRT1052.s for references
History:
1. Date: 2021-05-28
Author: AIIT XUOS Lab
Modification:
1. add OS entry function
*************************************************/
.syntax unified
.arch armv7-m
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* __noncachedata_start__/__noncachedata_end__ : none cachable region
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
ldr r2, =__noncachedata_start__
ldr r3, =__noncachedata_init_end__
#if 1
.LC2:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC2
#else
subs r3, r2
ble .LC3
.LC2:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC2
.LC3:
#endif
/* zero inited ncache section initialization */
ldr r3, =__noncachedata_end__
movs r0,0
.LC4:
cmp r2,r3
itt lt
strlt r0,[r2],#4
blt .LC4
#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC5:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC5
#endif /* __STARTUP_CLEAR_BSS */
ldr r0,=entry
blx r0
.size Reset_Handler, . - Reset_Handler

83
arch/arm/cortex-m7/interrupt.c

@ -0,0 +1,83 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file interrupt.c
* @brief support arm cortex-m4 interrupt function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
#include <xs_base.h>
#include <xs_isr.h>
x_base __attribute__((naked)) DisableLocalInterrupt()
{
asm volatile ("MRS r0, PRIMASK");
asm volatile ("CPSID I");
asm volatile ("BX LR ");
}
void __attribute__((naked)) EnableLocalInterrupt(x_base level)
{
asm volatile ("MSR PRIMASK, r0");
asm volatile ("BX LR");
}
int32 ArchEnableHwIrq(uint32 irq_num)
{
return EOK;
}
int32 ArchDisableHwIrq(uint32 irq_num)
{
return EOK;
}
extern void KTaskOsAssignAfterIrq(void *context);
void IsrEntry()
{
uint32 ipsr;
__asm__ volatile("MRS %0, IPSR" : "=r"(ipsr));
isrManager.done->incCounter();
isrManager.done->handleIrq(ipsr);
KTaskOsAssignAfterIrq(NONE);
isrManager.done->decCounter();
}
void UsageFault_Handler(int irqn, void *arg)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
void BusFault_Handler(int irqn, void *arg)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
void NMI_Handler(int irqn, void *arg)
{
while (1)
{
}
}

308
arch/arm/cortex-m7/interrupt_vector.S

@ -0,0 +1,308 @@
/* ------------------------------------------------------------------------- */
/* @file: startup_MIMXRT1052.s */
/* @purpose: CMSIS Cortex-M7 Core Device Startup File */
/* MIMXRT1052 */
/* @version: 1.0 */
/* @date: 2018-9-21 */
/* @build: b180921 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
/**
* @file interrupt_vector.S
* @brief vector table for Cortex M7
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
/*************************************************
File name: interrupt_vector.S
Description: vector table for a Cortex M7
Others:
History:
1. Date: 2021-05-28
Author: AIIT XUOS Lab
Modification:
1. add IsrEntry as default isr function
*************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFaultHandler /* Hard Fault Handler*/
.long MemFaultHandler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long IsrEntry /* SVCall Handler*/
.long IsrEntry /* Debug Monitor Handler*/
.long 0 /* Reserved*/
.long PendSV_Handler /* PendSV Handler*/
.long IsrEntry /* SysTick Handler*/
/* External Interrupts*/
.long IsrEntry /* DMA channel 0/16 transfer complete*/
.long IsrEntry /* DMA channel 1/17 transfer complete*/
.long IsrEntry /* DMA channel 2/18 transfer complete*/
.long IsrEntry /* DMA channel 3/19 transfer complete*/
.long IsrEntry /* DMA channel 4/20 transfer complete*/
.long IsrEntry /* DMA channel 5/21 transfer complete*/
.long IsrEntry /* DMA channel 6/22 transfer complete*/
.long IsrEntry /* DMA channel 7/23 transfer complete*/
.long IsrEntry /* DMA channel 8/24 transfer complete*/
.long IsrEntry /* DMA channel 9/25 transfer complete*/
.long IsrEntry /* DMA channel 10/26 transfer complete*/
.long IsrEntry /* DMA channel 11/27 transfer complete*/
.long IsrEntry /* DMA channel 12/28 transfer complete*/
.long IsrEntry /* DMA channel 13/29 transfer complete*/
.long IsrEntry /* DMA channel 14/30 transfer complete*/
.long IsrEntry /* DMA channel 15/31 transfer complete*/
.long IsrEntry /* DMA error interrupt channels 0-15 / 16-31*/
.long IsrEntry /* CTI0_Error*/
.long IsrEntry /* CTI1_Error*/
.long IsrEntry /* CorePlatform exception IRQ*/
.long IsrEntry /* LPUART1 TX interrupt and RX interrupt*/
.long IsrEntry /* LPUART2 TX interrupt and RX interrupt*/
.long IsrEntry /* LPUART3 TX interrupt and RX interrupt*/
.long IsrEntry /* LPUART4 TX interrupt and RX interrupt*/
.long IsrEntry /* LPUART5 TX interrupt and RX interrupt*/
.long IsrEntry /* LPUART6 TX interrupt and RX interrupt*/
.long IsrEntry /* LPUART7 TX interrupt and RX interrupt*/
.long IsrEntry /* LPUART8 TX interrupt and RX interrupt*/
.long IsrEntry /* LPI2C1 interrupt*/
.long IsrEntry /* LPI2C2 interrupt*/
.long IsrEntry /* LPI2C3 interrupt*/
.long IsrEntry /* LPI2C4 interrupt*/
.long IsrEntry /* LPSPI1 single interrupt vector for all sources*/
.long IsrEntry /* LPSPI2 single interrupt vector for all sources*/
.long IsrEntry /* LPSPI3 single interrupt vector for all sources*/
.long IsrEntry /* LPSPI4 single interrupt vector for all sources*/
.long IsrEntry /* CAN1 interrupt*/
.long IsrEntry /* CAN2 interrupt*/
.long IsrEntry /* FlexRAM address out of range Or access hit IRQ*/
.long IsrEntry /* Keypad nterrupt*/
.long IsrEntry /* TSC interrupt*/
.long IsrEntry /* GPR interrupt*/
.long IsrEntry /* LCDIF interrupt*/
.long IsrEntry /* CSI interrupt*/
.long IsrEntry /* PXP interrupt*/
.long IsrEntry /* WDOG2 interrupt*/
.long IsrEntry /* SRTC Consolidated Interrupt. Non TZ*/
.long IsrEntry /* SRTC Security Interrupt. TZ*/
.long IsrEntry /* ON-OFF button press shorter than 5 secs (pulse event)*/
.long IsrEntry /* CSU interrupt*/
.long IsrEntry /* DCP_IRQ interrupt*/
.long IsrEntry /* DCP_VMI_IRQ interrupt*/
.long IsrEntry /* Reserved interrupt*/
.long IsrEntry /* TRNG interrupt*/
.long IsrEntry /* SJC interrupt*/
.long IsrEntry /* BEE interrupt*/
.long IsrEntry /* SAI1 interrupt*/
.long IsrEntry /* SAI1 interrupt*/
.long IsrEntry /* SAI3 interrupt*/
.long IsrEntry /* SAI3 interrupt*/
.long IsrEntry /* SPDIF interrupt*/
.long IsrEntry /* Brown-out event interrupt*/
.long IsrEntry /* Reserved interrupt*/
.long IsrEntry /* TempSensor low/high interrupt*/
.long IsrEntry /* TempSensor panic interrupt*/
.long IsrEntry /* USBPHY (UTMI0), Interrupt*/
.long IsrEntry /* USBPHY (UTMI0), Interrupt*/
.long IsrEntry /* ADC1 interrupt*/
.long IsrEntry /* ADC2 interrupt*/
.long IsrEntry /* DCDC interrupt*/
.long IsrEntry /* Reserved interrupt*/
.long IsrEntry /* Reserved interrupt*/
.long IsrEntry /* Active HIGH Interrupt from INT0 from GPIO*/
.long IsrEntry /* Active HIGH Interrupt from INT1 from GPIO*/
.long IsrEntry /* Active HIGH Interrupt from INT2 from GPIO*/
.long IsrEntry /* Active HIGH Interrupt from INT3 from GPIO*/
.long IsrEntry /* Active HIGH Interrupt from INT4 from GPIO*/
.long IsrEntry /* Active HIGH Interrupt from INT5 from GPIO*/
.long IsrEntry /* Active HIGH Interrupt from INT6 from GPIO*/
.long IsrEntry /* Active HIGH Interrupt from INT7 from GPIO*/
.long IsrEntry /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/
.long IsrEntry /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/
.long IsrEntry /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/
.long IsrEntry /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/
.long IsrEntry /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/
.long IsrEntry /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/
.long IsrEntry /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/
.long IsrEntry /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/
.long IsrEntry /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/
.long IsrEntry /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/
.long IsrEntry /* FLEXIO1 interrupt*/
.long IsrEntry /* FLEXIO2 interrupt*/
.long IsrEntry /* WDOG1 interrupt*/
.long IsrEntry /* RTWDOG interrupt*/
.long IsrEntry /* EWM interrupt*/
.long IsrEntry /* CCM IRQ1 interrupt*/
.long IsrEntry /* CCM IRQ2 interrupt*/
.long IsrEntry /* GPC interrupt*/
.long IsrEntry /* SRC interrupt*/
.long IsrEntry /* Reserved interrupt*/
.long IsrEntry /* GPT1 interrupt*/
.long IsrEntry /* GPT2 interrupt*/
.long IsrEntry /* PWM1 capture 0, compare 0, or reload 0 interrupt*/
.long IsrEntry /* PWM1 capture 1, compare 1, or reload 0 interrupt*/
.long IsrEntry /* PWM1 capture 2, compare 2, or reload 0 interrupt*/
.long IsrEntry /* PWM1 capture 3, compare 3, or reload 0 interrupt*/
.long IsrEntry /* PWM1 fault or reload error interrupt*/
.long IsrEntry /* Reserved interrupt*/
.long IsrEntry /* FlexSPI0 interrupt*/
.long IsrEntry /* Reserved interrupt*/
.long IsrEntry /* USDHC1 interrupt*/
.long IsrEntry /* USDHC2 interrupt*/
.long IsrEntry /* USBO2 USB OTG2*/
.long IsrEntry /* USBO2 USB OTG1*/
.long IsrEntry /* ENET interrupt*/
.long IsrEntry /* ENET_1588_Timer interrupt*/
.long IsrEntry /* XBAR1 interrupt*/
.long IsrEntry /* XBAR1 interrupt*/
.long IsrEntry /* ADCETC IRQ0 interrupt*/
.long IsrEntry /* ADCETC IRQ1 interrupt*/
.long IsrEntry /* ADCETC IRQ2 interrupt*/
.long IsrEntry /* ADCETC Error IRQ interrupt*/
.long IsrEntry /* PIT interrupt*/
.long IsrEntry /* ACMP interrupt*/
.long IsrEntry /* ACMP interrupt*/
.long IsrEntry /* ACMP interrupt*/
.long IsrEntry /* ACMP interrupt*/
.long IsrEntry /* Reserved interrupt*/
.long IsrEntry /* Reserved interrupt*/
.long IsrEntry /* ENC1 interrupt*/
.long IsrEntry /* ENC2 interrupt*/
.long IsrEntry /* ENC3 interrupt*/
.long IsrEntry /* ENC4 interrupt*/
.long IsrEntry /* TMR1 interrupt*/
.long IsrEntry /* TMR2 interrupt*/
.long IsrEntry /* TMR3 interrupt*/
.long IsrEntry /* TMR4 interrupt*/
.long IsrEntry /* PWM2 capture 0, compare 0, or reload 0 interrupt*/
.long IsrEntry /* PWM2 capture 1, compare 1, or reload 0 interrupt*/
.long IsrEntry /* PWM2 capture 2, compare 2, or reload 0 interrupt*/
.long IsrEntry /* PWM2 capture 3, compare 3, or reload 0 interrupt*/
.long IsrEntry /* PWM2 fault or reload error interrupt*/
.long IsrEntry /* PWM3 capture 0, compare 0, or reload 0 interrupt*/
.long IsrEntry /* PWM3 capture 1, compare 1, or reload 0 interrupt*/
.long IsrEntry /* PWM3 capture 2, compare 2, or reload 0 interrupt*/
.long IsrEntry /* PWM3 capture 3, compare 3, or reload 0 interrupt*/
.long IsrEntry /* PWM3 fault or reload error interrupt*/
.long IsrEntry /* PWM4 capture 0, compare 0, or reload 0 interrupt*/
.long IsrEntry /* PWM4 capture 1, compare 1, or reload 0 interrupt*/
.long IsrEntry /* PWM4 capture 2, compare 2, or reload 0 interrupt*/
.long IsrEntry /* PWM4 capture 3, compare 3, or reload 0 interrupt*/
.long IsrEntry /* PWM4 fault or reload error interrupt*/
.long IsrEntry /* 168*/
.long IsrEntry /* 169*/
.long IsrEntry /* 170*/
.long IsrEntry /* 171*/
.long IsrEntry /* 172*/
.long IsrEntry /* 173*/
.long IsrEntry /* 174*/
.long IsrEntry /* 175*/
.long IsrEntry /* 176*/
.long IsrEntry /* 177*/
.long IsrEntry /* 178*/
.long IsrEntry /* 179*/
.long IsrEntry /* 180*/
.long IsrEntry /* 181*/
.long IsrEntry /* 182*/
.long IsrEntry /* 183*/
.long IsrEntry /* 184*/
.long IsrEntry /* 185*/
.long IsrEntry /* 186*/
.long IsrEntry /* 187*/
.long IsrEntry /* 188*/
.long IsrEntry /* 189*/
.long IsrEntry /* 190*/
.long IsrEntry /* 191*/
.long IsrEntry /* 192*/
.long IsrEntry /* 193*/
.long IsrEntry /* 194*/
.long IsrEntry /* 195*/
.long IsrEntry /* 196*/
.long IsrEntry /* 197*/
.long IsrEntry /* 198*/
.long IsrEntry /* 199*/
.long IsrEntry /* 200*/
.long IsrEntry /* 201*/
.long IsrEntry /* 202*/
.long IsrEntry /* 203*/
.long IsrEntry /* 204*/
.long IsrEntry /* 205*/
.long IsrEntry /* 206*/
.long IsrEntry /* 207*/
.long IsrEntry /* 208*/
.long IsrEntry /* 209*/
.long IsrEntry /* 210*/
.long IsrEntry /* 211*/
.long IsrEntry /* 212*/
.long IsrEntry /* 213*/
.long IsrEntry /* 214*/
.long IsrEntry /* 215*/
.long IsrEntry /* 216*/
.long IsrEntry /* 217*/
.long IsrEntry /* 218*/
.long IsrEntry /* 219*/
.long IsrEntry /* 220*/
.long IsrEntry /* 221*/
.long IsrEntry /* 222*/
.long IsrEntry /* 223*/
.long IsrEntry /* 224*/
.long IsrEntry /* 225*/
.long IsrEntry /* 226*/
.long IsrEntry /* 227*/
.long IsrEntry /* 228*/
.long IsrEntry /* 229*/
.long IsrEntry /* 230*/
.long IsrEntry /* 231*/
.long IsrEntry /* 232*/
.long IsrEntry /* 233*/
.long IsrEntry /* 234*/
.long IsrEntry /* 235*/
.long IsrEntry /* 236*/
.long IsrEntry /* 237*/
.long IsrEntry /* 238*/
.long IsrEntry /* 239*/
.long IsrEntry /* 240*/
.long IsrEntry /* 241*/
.long IsrEntry /* 242*/
.long IsrEntry /* 243*/
.long IsrEntry /* 244*/
.long IsrEntry /* 245*/
.long IsrEntry /* 246*/
.long IsrEntry /* 247*/
.long IsrEntry /* 248*/
.long IsrEntry /* 249*/
.long IsrEntry /* 250*/
.long IsrEntry /* 251*/
.long IsrEntry /* 252*/
.long IsrEntry /* 253*/
.long IsrEntry /* 254*/
.long 0xFFFFFFFF /* Reserved for user TRIM value*/
.size __isr_vector, . - __isr_vector
.text
.thumb

52
board/ok1052-c/Kconfig

@ -0,0 +1,52 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_CORTEX_M7_EVB
bool
select ARCH_ARM
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "ok1052-c feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "/XiUOS_ok1052C_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x2007F0000
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

5
board/ok1052-c/Makefile

@ -0,0 +1,5 @@
SRC_DIR := third_party_driver
SRC_FILES := board.c clock_config.c pin_mux.c
include $(KERNEL_ROOT)/compiler.mk

164
board/ok1052-c/README.md

@ -0,0 +1,164 @@
# 从零开始构建矽璓工业物联操作系统:使用ARM架构的ok1052-c
# ok1052-c
[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统,主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成,通过高效管理工业物联网设备、支撑工业物联应用,在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”,促进以工业设备和工业控制系统为核心的人、机、物深度互联,帮助提升生产线的数字化和智能化水平。
## 1. 简介
| 硬件 | 描述 |
| -- | -- |
|芯片型号| MIMXRT1052DVL6A |
|架构| cortex-m7 |
|主频| 600MHz |
|片内SRAM| 512KB shared with TCM |
|外设支持| UART |
XiUOS板级当前支持使用UART。
## 2. 开发环境搭建
### 推荐使用:
**操作系统:** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
更新`ubuntu 18.04`源的方法:(根据自身情况而定,可以不更改)
第一步:打开sources.list文件
```c
sudo vim /etc/apt/sources.list
```
第二步:将以下内容复制到sources.list文件
```c
deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
```
第三步:更新源和系统软件
```c
sudo apt-get update
sudo apt-get upgrade
```
**开发工具推荐使用 VSCode ,VScode下载地址为:** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/),推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
### 依赖包安装:
```
$ sudo apt install build-essential pkg-config git
$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
```
**XiUOS操作系统源码下载:** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
新建一个空文件夹并进入文件夹中,并下载源码,具体命令如下:
```c
mkdir test && cd test
git clone https://git.trustie.net/xuos/xiuos.git
```
打开源码文件包可以看到以下目录:
| 名称 | 说明 |
| -- | -- |
| application | 应用代码 |
| board | 板级支持包 |
| framework | 应用框架 |
| fs | 文件系统 |
| kernel | 内核源码 |
| resources | 驱动文件 |
| tool | 系统工具 |
使用VScode打开代码,具体操作步骤为:在源码文件夹下打开系统终端,输入`code .`即可打开VScode开发环境,如下图所示:
<div align= "center">
<img src = ./img/vscode.jpg width =1000>
</div>
### 裁减配置工具的下载
裁减配置工具:
**工具地址:** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends),下载与安装的具体命令如下:
```c
mkdir kfrontends && cd kfrontends
git clone https://git.trustie.net/xuos/kconfig-frontends.git
```
下载源码后按以下步骤执行软件安装:
```c
cd kconfig-frontends
./xs_build.sh
```
### 编译工具链:
ARM: arm-none-eabi(`gcc version 6.3.1`),默认安装到Ubuntu的/usr/bin/arm-none-eabi-,使用如下命令行下载和安装。
```shell
$ sudo apt install gcc-arm-none-eabi
```
## 编译说明
### 编辑环境:`Ubuntu18.04`
### 编译工具链:`arm-none-eabi-gcc`
使用`VScode`打开工程的方法有多种,本文介绍一种快捷键,在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
编译步骤:
1.在VScode命令终端中执行以下命令,生成配置文件
```c
make BOARD=ok1052-c menuconfig
```
2.在menuconfig界面配置需要关闭和开启的功能,按回车键进入下级菜单,按Y键选中需要开启的功能,按N键选中需要关闭的功能,配置结束后保存并退出(本例旨在演示简单的输出例程,所以没有需要配置的选项,双击快捷键ESC退出配置)
![menuconfig](./img/menuconfig.png)
退出时选择`yes`保存上面所配置的内容,如下图所示:
![menuconfig1](./img/menuconfig1.png)
3.继续执行以下命令,进行编译
```
make BOARD=ok1052-c
```
4.如果编译正确无误,会产生XiUOS_ok1052-c.elf、XiUOS_ok1052-c.bin文件。
## 3. 烧写及运行
### 3.1 烧写
1、烧写工具:NXP MCU Boot Utility,可参考[https://github.com/JayHeng/NXP-MCUBootUtility](https://github.com/JayHeng/NXP-MCUBootUtility)
2、ok1052-c开发板支持micro usb口烧写程序,打开NXP MCU Boot Utility后,选择好芯片类型为i.MXRT105x,开发板上电,使用usb线将开发板和PC连接,拨码开关设置为1 on 2 on 3 off 4 off,按下复位键K1后,若连接成功,可见Vendor ID和Product ID均有数字显示,点击reconnect,等待NXP MCU Boot Utility中红色显示变成蓝色显示,则表示已正确识别并连接到了开发板。如下图所示:
![NXPBootUtility_1](./img/NXPBootUtility_1.png)
3、选择编译生成的XiUOS_ok1052-c.elf文件路径,并选择.out(elf) from GCC ARM烧写选项,最后点击ALL-In-One Action即可烧写程序,若烧写无误,则下列绿色进度条会执行到底。如下图所示:
![NXPBootUtility_2](./img/NXPBootUtility_2.png)
### 3.2 运行结果
1、开发板支持rs232串口连接,使用rs232串口线或rs232转usb线将开发板和PC连接,使用串口终端工具可识别并连接开发板
2、按照3.1烧写步骤执行后,将拨码开关设置为1 off 2 off 3 off 4 off,按下复位键K1后,若程序正常,则串口终端上会显示启动信息打印输出。如下图所示:
![terminal](./img/terminal.png)

184
board/ok1052-c/board.c

@ -0,0 +1,184 @@
/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/**
* @file board.c
* @brief support imxrt1052-board init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-29
*/
/*************************************************
File name: board.c
Description: support imxrt1052-board init configure and driver/task/... init
Others: take SDK_2.6.1_MIMXRT1052xxxxB/devices/MIMXRT1052/project_template/board.c
History:
1. Date: 2021-05-29
Author: AIIT XUOS Lab
Modification:
1. support imxrt1052-board InitBoardHardware
*************************************************/
#include "board.h"
#include "pin_mux.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include <connect_uart.h>
#include "fsl_lpuart.h"
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/* MPU configuration. */
static void BOARD_ConfigMPU(void)
{
/* Disable I cache and D cache */
SCB_DisableICache();
SCB_DisableDCache();
/* Disable MPU */
ARM_MPU_Disable();
/* Region 0 setting */
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 1 setting */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 2 setting */
// spi flash: normal type, cacheable, no bufferable, no shareable
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 3 setting */
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 4 setting */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 5 setting */
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
/* Region 6 setting */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
#if defined(BSP_USING_SDRAM)
/* Region 7 setting */
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
/* Region 8 setting */
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
#endif
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
/* Enable I cache and D cache */
SCB_EnableDCache();
SCB_EnableICache();
}
/* This is the timer interrupt service routine. */
void SysTick_Handler(int irqn, void *arg)
{
TickAndTaskTimesliceUpdate();
}
DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
#ifdef BSP_USING_LPUART
void imxrt_uart_pins_init(void)
{
#ifdef BSP_USING_LPUART1
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
#endif
#ifdef BSP_USING_LPUART2
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0x10B0u);
#endif
}
#endif /* BSP_USING_LPUART */
/**
* This function will initial rt1050 board.
*/
void InitBoardHardware()
{
BOARD_ConfigMPU();
BOARD_InitPins();
BOARD_BootClockRUN();
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
SysTick_Config(SystemCoreClock / TICK_PER_SECOND);
#ifdef BSP_USING_LPUART
imxrt_uart_pins_init();
#endif
InitBoardMemory((void *)HEAP_BEGIN, (void *)HEAP_END);
Imrt1052HwUartInit();
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
}

52
board/ok1052-c/board.h

@ -0,0 +1,52 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.h
* @brief define imxrt1052-board init configure and start-up function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
/*************************************************
File name: board.h
Description: define imxrt1052-board board init function and struct
Others:
History:
1. Date: 2021-05-28
Author: AIIT XUOS Lab
Modification:
1. define imxrt-board InitBoardHardware
2. define imxrt-board heap struct
*************************************************/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "fsl_common.h"
#include "clock_config.h"
#include <xiuos.h>
#include <arch_interrupt.h>
extern int heap_start;
extern int heap_end;
#define HEAP_BEGIN (&heap_start)
#define HEAP_END (&heap_end)
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
void InitBoardHardware(void);
#endif

479
board/ok1052-c/clock_config.c

@ -0,0 +1,479 @@
/*
* Copyright 2017-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/**
* @file clock_config.c
* @brief support imxrt1052-board clock configure
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-29
*/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v5.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 5.0.2
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.LCDIF_PODF.scale, value: '8', locked: true}
- {id: CCM.LCDIF_PRED.scale, value: '7', locked: true}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
- {id: CCM_ANALOG.PLL5.div, value: '40'}
- {id: CCM_ANALOG.PLL5.num, value: '0'}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
CLOCK_DisableClock(kCLOCK_Xbar3);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
/* Set CSI_PODF. */
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
/* Set Csi clock source. */
CLOCK_SetMux(kCLOCK_CsiMux, 0);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 2);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 6);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 7);
/* Set Lcdif pre clock source. */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Disable Flexio2 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio2);
/* Set FLEXIO2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
/* Set FLEXIO2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
/* Set Flexio2 clock source. */
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
/* Disable pfd offset. */
CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();