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Add extern sram support on stm32f407zgt6 for XiUOS

it is perfect
pull/3/head
xuedongliang 1 year ago
parent
commit
92301257f3
  1. 4
      arch/arm/cortex-m4/system_init.c
  2. 8
      board/aiit-arm32-board/board.c
  3. 1
      board/aiit-arm32-board/third_party_driver/Kconfig
  4. 17
      board/aiit-arm32-board/third_party_driver/extmem/Kconfig
  5. 2
      board/aiit-arm32-board/third_party_driver/extmem/Makefile
  6. 162
      board/aiit-arm32-board/third_party_driver/extmem/connect_fsmc.c
  7. 336
      board/aiit-arm32-board/third_party_driver/extmem/extmem.c
  8. 1101
      board/aiit-arm32-board/third_party_driver/extmem/hardware_fsmc.c
  9. 24
      board/aiit-arm32-board/third_party_driver/include/connect_fsmc.h
  10. 1
      board/aiit-arm32-board/third_party_driver/include/hardware_fsmc.h
  11. 7
      board/stm32f407-st-discovery/third_party_driver/Kconfig
  12. 5
      board/stm32f407-st-discovery/third_party_driver/Makefile
  13. 0
      board/stm32f407-st-discovery/third_party_driver/extmem/Kconfig
  14. 3
      board/stm32f407-st-discovery/third_party_driver/extmem/Makefile
  15. 336
      board/stm32f407-st-discovery/third_party_driver/extmem/extmem.c
  16. 6
      board/stm32f407zgt6/board.c
  17. 7
      board/stm32f407zgt6/third_party_driver/Kconfig
  18. 3
      board/stm32f407zgt6/third_party_driver/Makefile
  19. 17
      board/stm32f407zgt6/third_party_driver/extmem/Kconfig
  20. 3
      board/stm32f407zgt6/third_party_driver/extmem/Makefile
  21. 162
      board/stm32f407zgt6/third_party_driver/extmem/connect_fsmc.c
  22. 1101
      board/stm32f407zgt6/third_party_driver/extmem/hardware_fsmc.c
  23. 26
      board/stm32f407zgt6/third_party_driver/include/connect_fsmc.h
  24. 689
      board/stm32f407zgt6/third_party_driver/include/hardware_fsmc.h
  25. 4
      kernel/Kconfig
  26. 3
      kernel/include/xs_memory.h
  27. 5
      kernel/kernel_test/Makefile
  28. 79
      kernel/kernel_test/extsram_test.c
  29. 2
      kernel/kernel_test/test_mem.c
  30. 270
      kernel/memory/byte_manage.c

4
arch/arm/cortex-m4/system_init.c

@ -91,10 +91,6 @@ void SystemInit(void)
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInitExtMemCtl();
#endif
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
#else

8
board/aiit-arm32-board/board.c

@ -47,6 +47,7 @@ extern int Stm32HwRtcInit();
extern int Stm32HwTouchBusInit(void);
extern int Stm32HwCanBusInit(void);
extern int HwSdioInit();
extern int HwSramInit(void);
static void ClockConfiguration()
{
@ -142,6 +143,9 @@ struct InitSequenceDesc _board_init[] =
#endif
#ifdef BSP_USING_SDIO
{"hw sdcard init",HwSdioInit},
#endif
#ifdef BSP_USING_EXTMEM
{ "hw extern sram", HwSramInit },
#endif
{ " NONE ",NONE },
};
@ -155,16 +159,18 @@ void InitBoardHardware()
NVIC_Configuration();
SysTickConfiguration();
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
#ifdef BSP_USING_UART
Stm32HwUsartInit();
#endif
#ifdef KERNEL_CONSOLE
InstallConsole(KERNEL_CONSOLE_BUS_NAME, KERNEL_CONSOLE_DRV_NAME, KERNEL_CONSOLE_DEVICE_NAME);
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
#ifdef SEPARATE_COMPILE

1
board/aiit-arm32-board/third_party_driver/Kconfig

@ -15,6 +15,7 @@ endif
menuconfig BSP_USING_EXTMEM
bool "Using EXTMEM device"
default n
select MEM_EXTERN_SRAM
if BSP_USING_EXTMEM
source "$BSP_DIR/third_party_driver/extmem/Kconfig"
endif

17
board/aiit-arm32-board/third_party_driver/extmem/Kconfig

@ -0,0 +1,17 @@
if BSP_USING_EXTMEM
config EXTSRAM_MAX_NUM
int
default 4
config BSP_USING_FSMC_BANK1_NORSRAM3
bool "config fsmc bank1 sram3"
default n
if BSP_USING_FSMC_BANK1_NORSRAM3
config BANK1_NORSRAM3_SIZE
hex "config sram3 chip size"
default 0x100000
config BANK1_NORSRAM3_DATA_WIDTH
int "config sram3 chip data width"
default 16
endif
endif

2
board/aiit-arm32-board/third_party_driver/extmem/Makefile

@ -1,3 +1,3 @@
SRC_FILES := extmem.c
SRC_FILES := hardware_fsmc.c connect_fsmc.c
include $(KERNEL_ROOT)/compiler.mk

162
board/aiit-arm32-board/third_party_driver/extmem/connect_fsmc.c

@ -0,0 +1,162 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_fsmc.c
* @brief support extern memory by fsmc
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
#include "connect_fsmc.h"
#include "hardware_fsmc.h"
#include "hardware_gpio.h"
#include "hardware_rcc.h"
#include <string.h>
#include <xs_base.h>
#define FSMC_BANK1_NORSRAM3_START_ADDRESS 0x68000000
static FSMC_NORSRAMInitTypeDef hsram3;
static FSMC_NORSRAMTimingInitTypeDef hsram_read3;
static FSMC_NORSRAMTimingInitTypeDef hsram_write3;
extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx);
int HwSramInit(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE);
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOE, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOF, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOG, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC);
hsram3.FSMC_ReadWriteTimingStruct = &hsram_read3;
hsram3.FSMC_WriteTimingStruct = &hsram_write3;
/* hsram3.Init */
hsram3.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
hsram3.FSMC_MemoryType = FSMC_MemoryType_SRAM;
hsram3.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
hsram3.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
hsram3.FSMC_WrapMode = FSMC_WrapMode_Disable;
hsram3.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
hsram3.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
hsram3.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
hsram3.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
hsram3.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
hsram_read3.FSMC_AddressSetupTime = 0;
hsram_read3.FSMC_AddressHoldTime = 0;
hsram_read3.FSMC_DataSetupTime = 8;
hsram_read3.FSMC_BusTurnAroundDuration = 0;
hsram_read3.FSMC_CLKDivision = 0;
hsram_read3.FSMC_DataLatency = 0;
hsram_read3.FSMC_AccessMode = FSMC_AccessMode_A;
hsram_write3.FSMC_AddressSetupTime = 0;
hsram_write3.FSMC_AddressHoldTime = 0;
hsram_write3.FSMC_DataSetupTime = 8;
hsram_write3.FSMC_BusTurnAroundDuration = 0;
hsram_write3.FSMC_CLKDivision = 0;
hsram_write3.FSMC_DataLatency = 0;
hsram_write3.FSMC_AccessMode = FSMC_AccessMode_A;
#ifdef BSP_USING_FSMC_BANK1_NORSRAM3
hsram3.FSMC_Bank = FSMC_Bank1_NORSRAM3;
#if BANK1_NORSRAM3_DATA_WIDTH == 8
hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
#elif BANK1_NORSRAM3_DATA_WIDTH == 16
hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
#else
hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
#endif
FSMC_NORSRAMInit(&hsram3);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
ExtSramInitBoardMemory((void*)(FSMC_BANK1_NORSRAM3_START_ADDRESS), (void*)((FSMC_BANK1_NORSRAM3_START_ADDRESS + BANK1_NORSRAM3_SIZE)), 2);
#endif
return 0;
}

336
board/aiit-arm32-board/third_party_driver/extmem/extmem.c

@ -1,336 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file extmem.c
* @brief support extmem function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
#include <extmem.h>
#include <stm32f4xx.h>
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
void SystemInitExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
RCC->AHB1ENR |= 0x000001F8;
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
GPIOD->MODER = 0xAAAA0A8A;
GPIOD->OSPEEDR = 0xFFFF0FCF;
GPIOD->OTYPER = 0x00000000;
GPIOD->PUPDR = 0x00000000;
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
GPIOE->MODER = 0xAAAA828A;
GPIOE->OSPEEDR = 0xFFFFC3CF;
GPIOE->OTYPER = 0x00000000;
GPIOE->PUPDR = 0x00000000;
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
GPIOF->MODER = 0xAA800AAA;
GPIOF->OSPEEDR = 0xAA800AAA;
GPIOF->OTYPER = 0x00000000;
GPIOF->PUPDR = 0x00000000;
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
GPIOG->MODER = 0xAAAAAAAA;
GPIOG->OSPEEDR = 0xAAAAAAAA;
GPIOG->OTYPER = 0x00000000;
GPIOG->PUPDR = 0x00000000;
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
GPIOH->MODER = 0xAAAA08A0;
GPIOH->OSPEEDR = 0xAAAA08A0;
GPIOH->OTYPER = 0x00000000;
GPIOH->PUPDR = 0x00000000;
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
GPIOI->MODER = 0x0028AAAA;
GPIOI->OSPEEDR = 0x0028AAAA;
GPIOI->OTYPER = 0x00000000;
GPIOI->PUPDR = 0x00000000;
RCC->AHB3ENR |= 0x00000001;
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
for (index = 0; index<1000; index++);
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
#if defined(STM32F469xx) || defined(STM32F479xx)
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
(void)(tmp);
}
#endif
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
void SystemInitExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
#if defined(STM32F446xx)
RCC->AHB1ENR |= 0x0000007D;
#else
RCC->AHB1ENR |= 0x000001F8;
#endif
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
#if defined(STM32F446xx)
GPIOA->AFR[0] |= 0xC0000000;
GPIOA->AFR[1] |= 0x00000000;
GPIOA->MODER |= 0x00008000;
GPIOA->OSPEEDR |= 0x00008000;
GPIOA->OTYPER |= 0x00000000;
GPIOA->PUPDR |= 0x00000000;
GPIOC->AFR[0] |= 0x00CC0000;
GPIOC->AFR[1] |= 0x00000000;
GPIOC->MODER |= 0x00000A00;
GPIOC->OSPEEDR |= 0x00000A00;
GPIOC->OTYPER |= 0x00000000;
GPIOC->PUPDR |= 0x00000000;
#endif
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
GPIOD->MODER = 0xA02A000A;
GPIOD->OSPEEDR = 0xA02A000A;
GPIOD->OTYPER = 0x00000000;
GPIOD->PUPDR = 0x00000000;
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
GPIOE->MODER = 0xAAAA800A;
GPIOE->OSPEEDR = 0xAAAA800A;
GPIOE->OTYPER = 0x00000000;
GPIOE->PUPDR = 0x00000000;
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
GPIOF->MODER = 0xAA800AAA;
GPIOF->OSPEEDR = 0xAA800AAA;
GPIOF->OTYPER = 0x00000000;
GPIOF->PUPDR = 0x00000000;
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
GPIOG->MODER = 0xAAAAAAAA;
GPIOG->OSPEEDR = 0xAAAAAAAA;
GPIOG->OTYPER = 0x00000000;
GPIOG->PUPDR = 0x00000000;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
GPIOH->MODER = 0xAAAA08A0;
GPIOH->OSPEEDR = 0xAAAA08A0;
GPIOH->OTYPER = 0x00000000;
GPIOH->PUPDR = 0x00000000;
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
GPIOI->MODER = 0x0028AAAA;
GPIOI->OSPEEDR = 0x0028AAAA;
GPIOI->OTYPER = 0x00000000;
GPIOI->PUPDR = 0x00000000;
#endif
RCC->AHB3ENR |= 0x00000001;
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
#if defined(STM32F446xx)
FMC_Bank5_6->SDCR[0] = 0x00001954;
#else
FMC_Bank5_6->SDCR[0] = 0x000019E4;
#endif
FMC_Bank5_6->SDTR[0] = 0x01115351;
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
for (index = 0; index<1000; index++);
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x000000F3;
#else
FMC_Bank5_6->SDCMR = 0x00000073;
#endif
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x00044014;
#else
FMC_Bank5_6->SDCMR = 0x00046014;
#endif
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
tmpreg = FMC_Bank5_6->SDRTR;
#if defined(STM32F446xx)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
#else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
#endif
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif
#endif
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
#if defined(DATA_IN_ExtSRAM)
RCC->AHB1ENR |= 0x00000078;
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
GPIOD->MODER = 0xAAAA0A8A;
GPIOD->OSPEEDR = 0xFFFF0FCF;
GPIOD->OTYPER = 0x00000000;
GPIOD->PUPDR = 0x00000000;
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
GPIOE->MODER = 0xAAAA828A;
GPIOE->OSPEEDR = 0xFFFFC3CF;
GPIOE->OTYPER = 0x00000000;
GPIOE->PUPDR = 0x00000000;
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
GPIOF->MODER = 0xAA000AAA;
GPIOF->OSPEEDR = 0xFF000FFF;
GPIOF->OTYPER = 0x00000000;
GPIOF->PUPDR = 0x00000000;
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
GPIOG->MODER = 0x00085AAA;
GPIOG->OSPEEDR = 0x000CAFFF;
GPIOG->OTYPER = 0x00000000;
GPIOG->PUPDR = 0x00000000;
RCC->AHB3ENR |= 0x00000001;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
#if defined(STM32F469xx) || defined(STM32F479xx)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
#endif
#endif
#endif
(void)(tmp);
}
#endif

1101
board/aiit-arm32-board/third_party_driver/extmem/hardware_fsmc.c

File diff suppressed because it is too large

24
board/aiit-arm32-board/third_party_driver/include/extmem.h → board/aiit-arm32-board/third_party_driver/include/connect_fsmc.h

@ -9,20 +9,28 @@
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file extmem.h
* @brief support extmem function
* @file connect_fsmc.h
* @brief declare stm32f407zgt6-board fsmc function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
* @date 2021-05-28
*/
#ifndef EXTMEM_H
#define EXTMEM_H
#ifndef CONNECT_FSMC_H
#define CONNECT_FSMC_H
#include <xsconfig.h>
#ifdef __cplusplus
extern "C" {
#endif
int HwSramInit(void);
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
void SystemInitExtMemCtl(void);
#ifdef __cplusplus
}
#endif
#endif

1
board/aiit-arm32-board/third_party_driver/include/hardware_fsmc.h

@ -334,6 +334,7 @@ typedef struct
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define FSMC_MemoryDataWidth_32b ((uint32_t)0x00000020)
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
((WIDTH) == FSMC_MemoryDataWidth_16b))
/**

7
board/stm32f407-st-discovery/third_party_driver/Kconfig

@ -13,13 +13,6 @@ if BSP_USING_DMA
source "$BSP_DIR/third_party_driver/common/Kconfig"
endif
menuconfig BSP_USING_EXTMEM
bool "Using EXTMEM device"
default n
if BSP_USING_EXTMEM
source "$BSP_DIR/third_party_driver/extmem/Kconfig"
endif
menuconfig BSP_USING_GPIO
bool "Using GPIO device "
default y

5
board/stm32f407-st-discovery/third_party_driver/Makefile

@ -5,11 +5,6 @@ ifeq ($(CONFIG_BSP_USING_CAN),y)
SRC_DIR += can
endif
ifeq ($(CONFIG_BSP_USING_EXTMEM),y)
SRC_DIR += extmem
endif
ifeq ($(CONFIG_BSP_USING_GPIO),y)
SRC_DIR += gpio
endif

0
board/stm32f407-st-discovery/third_party_driver/extmem/Kconfig

3
board/stm32f407-st-discovery/third_party_driver/extmem/Makefile

@ -1,3 +0,0 @@
SRC_FILES := extmem.c
include $(KERNEL_ROOT)/compiler.mk

336
board/stm32f407-st-discovery/third_party_driver/extmem/extmem.c

@ -1,336 +0,0 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file extmem.c
* @brief support extmem function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
*/
#include "stm32f4xx.h"
#include "extmem.h"
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
void SystemInitExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
RCC->AHB1ENR |= 0x000001F8;
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
GPIOD->MODER = 0xAAAA0A8A;
GPIOD->OSPEEDR = 0xFFFF0FCF;
GPIOD->OTYPER = 0x00000000;
GPIOD->PUPDR = 0x00000000;
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
GPIOE->MODER = 0xAAAA828A;
GPIOE->OSPEEDR = 0xFFFFC3CF;
GPIOE->OTYPER = 0x00000000;
GPIOE->PUPDR = 0x00000000;
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
GPIOF->MODER = 0xAA800AAA;
GPIOF->OSPEEDR = 0xAA800AAA;
GPIOF->OTYPER = 0x00000000;
GPIOF->PUPDR = 0x00000000;
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
GPIOG->MODER = 0xAAAAAAAA;
GPIOG->OSPEEDR = 0xAAAAAAAA;
GPIOG->OTYPER = 0x00000000;
GPIOG->PUPDR = 0x00000000;
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
GPIOH->MODER = 0xAAAA08A0;
GPIOH->OSPEEDR = 0xAAAA08A0;
GPIOH->OTYPER = 0x00000000;
GPIOH->PUPDR = 0x00000000;
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
GPIOI->MODER = 0x0028AAAA;
GPIOI->OSPEEDR = 0x0028AAAA;
GPIOI->OTYPER = 0x00000000;
GPIOI->PUPDR = 0x00000000;
RCC->AHB3ENR |= 0x00000001;
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
for (index = 0; index<1000; index++);
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
FMC_Bank5_6->SDCMR = 0x00000073;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
#if defined(STM32F469xx) || defined(STM32F479xx)
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
(void)(tmp);
}
#endif
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
void SystemInitExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
#if defined(STM32F446xx)
RCC->AHB1ENR |= 0x0000007D;
#else
RCC->AHB1ENR |= 0x000001F8;
#endif
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
#if defined(STM32F446xx)
GPIOA->AFR[0] |= 0xC0000000;
GPIOA->AFR[1] |= 0x00000000;
GPIOA->MODER |= 0x00008000;
GPIOA->OSPEEDR |= 0x00008000;
GPIOA->OTYPER |= 0x00000000;
GPIOA->PUPDR |= 0x00000000;
GPIOC->AFR[0] |= 0x00CC0000;
GPIOC->AFR[1] |= 0x00000000;
GPIOC->MODER |= 0x00000A00;
GPIOC->OSPEEDR |= 0x00000A00;
GPIOC->OTYPER |= 0x00000000;
GPIOC->PUPDR |= 0x00000000;
#endif
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
GPIOD->MODER = 0xA02A000A;
GPIOD->OSPEEDR = 0xA02A000A;
GPIOD->OTYPER = 0x00000000;
GPIOD->PUPDR = 0x00000000;
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
GPIOE->MODER = 0xAAAA800A;
GPIOE->OSPEEDR = 0xAAAA800A;
GPIOE->OTYPER = 0x00000000;
GPIOE->PUPDR = 0x00000000;
GPIOF->AFR[0] = 0xCCCCCCCC;
GPIOF->AFR[1] = 0xCCCCCCCC;
GPIOF->MODER = 0xAA800AAA;
GPIOF->OSPEEDR = 0xAA800AAA;
GPIOF->OTYPER = 0x00000000;
GPIOF->PUPDR = 0x00000000;
GPIOG->AFR[0] = 0xCCCCCCCC;
GPIOG->AFR[1] = 0xCCCCCCCC;
GPIOG->MODER = 0xAAAAAAAA;
GPIOG->OSPEEDR = 0xAAAAAAAA;
GPIOG->OTYPER = 0x00000000;
GPIOG->PUPDR = 0x00000000;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx)
GPIOH->AFR[0] = 0x00C0CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
GPIOH->MODER = 0xAAAA08A0;
GPIOH->OSPEEDR = 0xAAAA08A0;
GPIOH->OTYPER = 0x00000000;
GPIOH->PUPDR = 0x00000000;
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
GPIOI->MODER = 0x0028AAAA;
GPIOI->OSPEEDR = 0x0028AAAA;
GPIOI->OTYPER = 0x00000000;
GPIOI->PUPDR = 0x00000000;
#endif
RCC->AHB3ENR |= 0x00000001;
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
#if defined(STM32F446xx)
FMC_Bank5_6->SDCR[0] = 0x00001954;
#else
FMC_Bank5_6->SDCR[0] = 0x000019E4;
#endif
FMC_Bank5_6->SDTR[0] = 0x01115351;
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
for (index = 0; index<1000; index++);
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x000000F3;
#else
FMC_Bank5_6->SDCMR = 0x00000073;
#endif
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
#if defined(STM32F446xx)
FMC_Bank5_6->SDCMR = 0x00044014;
#else
FMC_Bank5_6->SDCMR = 0x00046014;
#endif
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
tmpreg = FMC_Bank5_6->SDRTR;
#if defined(STM32F446xx)
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
#else
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
#endif
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
#endif
#endif
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
#if defined(DATA_IN_ExtSRAM)
RCC->AHB1ENR |= 0x00000078;
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
GPIOD->MODER = 0xAAAA0A8A;
GPIOD->OSPEEDR = 0xFFFF0FCF;
GPIOD->OTYPER = 0x00000000;
GPIOD->PUPDR = 0x00000000;
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
GPIOE->MODER = 0xAAAA828A;
GPIOE->OSPEEDR = 0xFFFFC3CF;
GPIOE->OTYPER = 0x00000000;
GPIOE->PUPDR = 0x00000000;
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
GPIOF->MODER = 0xAA000AAA;
GPIOF->OSPEEDR = 0xFF000FFF;
GPIOF->OTYPER = 0x00000000;
GPIOF->PUPDR = 0x00000000;
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
GPIOG->MODER = 0x00085AAA;
GPIOG->OSPEEDR = 0x000CAFFF;
GPIOG->OTYPER = 0x00000000;
GPIOG->PUPDR = 0x00000000;
RCC->AHB3ENR |= 0x00000001;
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
#if defined(STM32F469xx) || defined(STM32F479xx)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
FMC_Bank1->BTCR[2] = 0x00001091;
FMC_Bank1->BTCR[3] = 0x00110212;
FMC_Bank1E->BWTR[2] = 0x0fffffff;
#endif
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|| defined(STM32F412Zx) || defined(STM32F412Vx)
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
#endif
#endif
#endif
(void)(tmp);
}
#endif

6
board/stm32f407zgt6/board.c

@ -35,6 +35,7 @@ Modification:
#include "board.h"
#include "connect_usart.h"
#include "connect_gpio.h"
#include "connect_fsmc.h"
#include "misc.h"
extern void entry(void);
@ -104,6 +105,9 @@ struct InitSequenceDesc _board_init[] =
{
#ifdef BSP_USING_GPIO
{ "hw pin", Stm32HwGpioInit },
#endif
#ifdef BSP_USING_EXTMEM
{ "hw extern sram", HwSramInit },
#endif
{ " NONE ",NONE },
};
@ -117,6 +121,7 @@ void InitBoardHardware()
NVIC_Configuration();
SysTickConfiguration();
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
#ifdef BSP_USING_UART
Stm32HwUsartInit();
#endif
@ -125,7 +130,6 @@ void InitBoardHardware()
KPrintf("\nconsole init completed.\n");
KPrintf("board initialization......\n");
#endif
InitBoardMemory((void*)MEMORY_START_ADDRESS, (void*)MEMORY_END_ADDRESS);
#ifdef SEPARATE_COMPILE

7
board/stm32f407zgt6/third_party_driver/Kconfig

@ -15,3 +15,10 @@ if BSP_USING_UART
source "$BSP_DIR/third_party_driver/uart/Kconfig"
endif
menuconfig BSP_USING_EXTMEM
bool "Using extern memory"
default n
select MEM_EXTERN_SRAM
if BSP_USING_EXTMEM
source "$BSP_DIR/third_party_driver/extmem/Kconfig"
endif

3
board/stm32f407zgt6/third_party_driver/Makefile

@ -9,5 +9,8 @@ ifeq ($(CONFIG_BSP_USING_UART),y)
SRC_DIR += uart
endif
ifeq ($(CONFIG_BSP_USING_EXTMEM),y)
SRC_DIR += extmem
endif
include $(KERNEL_ROOT)/compiler.mk

17
board/stm32f407zgt6/third_party_driver/extmem/Kconfig

@ -0,0 +1,17 @@
if BSP_USING_EXTMEM
config EXTSRAM_MAX_NUM
int
default 4
config BSP_USING_FSMC_BANK1_NORSRAM3
bool "config fsmc bank1 sram3"
default n
if BSP_USING_FSMC_BANK1_NORSRAM3
config BANK1_NORSRAM3_SIZE
hex "config sram3 chip size"
default 0x100000
config BANK1_NORSRAM3_DATA_WIDTH
int "config sram3 chip data width"
default 16
endif
endif

3
board/stm32f407zgt6/third_party_driver/extmem/Makefile

@ -0,0 +1,3 @@
SRC_FILES := hardware_fsmc.c connect_fsmc.c
include $(KERNEL_ROOT)/compiler.mk

162
board/stm32f407zgt6/third_party_driver/extmem/connect_fsmc.c

@ -0,0 +1,162 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file connect_fsmc.c
* @brief support extern memory by fsmc
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-05-28
*/
#include "connect_fsmc.h"
#include "hardware_fsmc.h"
#include "hardware_gpio.h"
#include "hardware_rcc.h"
#include <string.h>
#include <xs_base.h>
#define FSMC_BANK1_NORSRAM3_START_ADDRESS 0x68000000
static FSMC_NORSRAMInitTypeDef hsram3;
static FSMC_NORSRAMTimingInitTypeDef hsram_read3;
static FSMC_NORSRAMTimingInitTypeDef hsram_write3;
extern void ExtSramInitBoardMemory(void *start_phy_address, void *end_phy_address, uint8 extsram_idx);
int HwSramInit(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE);
RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC,ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOE, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOF, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_10 | GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOG, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOG,GPIO_PinSource12,GPIO_AF_FSMC);
hsram3.FSMC_ReadWriteTimingStruct = &hsram_read3;
hsram3.FSMC_WriteTimingStruct = &hsram_write3;
/* hsram3.Init */
hsram3.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
hsram3.FSMC_MemoryType = FSMC_MemoryType_SRAM;
hsram3.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
hsram3.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
hsram3.FSMC_WrapMode = FSMC_WrapMode_Disable;
hsram3.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
hsram3.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
hsram3.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
hsram3.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
hsram3.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
hsram_read3.FSMC_AddressSetupTime = 0;
hsram_read3.FSMC_AddressHoldTime = 0;
hsram_read3.FSMC_DataSetupTime = 8;
hsram_read3.FSMC_BusTurnAroundDuration = 0;
hsram_read3.FSMC_CLKDivision = 0;
hsram_read3.FSMC_DataLatency = 0;
hsram_read3.FSMC_AccessMode = FSMC_AccessMode_A;
hsram_write3.FSMC_AddressSetupTime = 0;
hsram_write3.FSMC_AddressHoldTime = 0;
hsram_write3.FSMC_DataSetupTime = 8;
hsram_write3.FSMC_BusTurnAroundDuration = 0;
hsram_write3.FSMC_CLKDivision = 0;
hsram_write3.FSMC_DataLatency = 0;
hsram_write3.FSMC_AccessMode = FSMC_AccessMode_A;
#ifdef BSP_USING_FSMC_BANK1_NORSRAM3
hsram3.FSMC_Bank = FSMC_Bank1_NORSRAM3;
#if BANK1_NORSRAM3_DATA_WIDTH == 8
hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
#elif BANK1_NORSRAM3_DATA_WIDTH == 16
hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
#else
hsram3.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_32b;
#endif
FSMC_NORSRAMInit(&hsram3);
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
ExtSramInitBoardMemory((void*)(FSMC_BANK1_NORSRAM3_START_ADDRESS), (void*)((FSMC_BANK1_NORSRAM3_START_ADDRESS + BANK1_NORSRAM3_SIZE)), 2);
#endif
return 0;
}

1101
board/stm32f407zgt6/third_party_driver/extmem/hardware_fsmc.c

File diff suppressed because it is too large

26
board/stm32f407-st-discovery/third_party_driver/include/extmem.h → board/stm32f407zgt6/third_party_driver/include/connect_fsmc.h

@ -1,6 +1,6 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* xiuOS is licensed under Mulan PSL v2.
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
@ -9,20 +9,28 @@
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file extmem.h
* @brief support extmem function
* @file connect_fsmc.h
* @brief declare stm32f407zgt6-board fsmc function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-04-25
* @date 2021-05-28
*/
#ifndef EXTMEM_H
#define EXTMEM_H
#ifndef CONNECT_FSMC_H
#define CONNECT_FSMC_H
#include <xsconfig.h>
#ifdef __cplusplus
extern "C" {
#endif
int HwSramInit(void);
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
void SystemInitExtMemCtl(void);
#ifdef __cplusplus
}
#endif
#endif

689
board/stm32f407zgt6/third_party_driver/include/hardware_fsmc.h

@ -0,0 +1,689 @@
/**
******************************************************************************
* @file stm32f4xx_fsmc.h
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/**
* @file: hardware_fsmc.h
* @brief: define hardware fsmc function
* @version: 1.0
* @author: AIIT XUOS Lab
* @date: 2021/4/25
*/
/*************************************************
File name: hardware_fsmc.h
Description: define hardware fsmc function
Others:
History:
1. Date: 2021-04-25
Author: AIIT XUOS Lab
Modification:
1. rename stm32f4xx_fsmc.h for XiUOS
*************************************************/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HARDWARE_FSMC_H__
#define __HARDWARE_FSMC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stm32f4xx.h>
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @addtogroup FSMC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief Timing parameters For NOR/SRAM Banks
*/
typedef struct
{
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between 0 and 0xF.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between 0 and 0xF.
@note This parameter is not used with synchronous NOR Flash memories.*/
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between 0 and 0xFF.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between 0 and 0xF.
@note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
This parameter can be a value between 1 and 0xF.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between 0 and 0xF in NOR Flash memories
with synchronous burst mode enable */
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
}FSMC_NORSRAMTimingInitTypeDef;
/**
* @brief FSMC NOR/SRAM Init structure definition
*/
typedef struct
{
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the databus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory bank.
This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_Data_Width */
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
}FSMC_NORSRAMInitTypeDef;
/**
* @brief Timing parameters For FSMC NAND and PCCARD Banks
*/
typedef struct
{
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
</