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add gapuino board of gap8

it is Perfect
master
xuedongliang 10 months ago
parent
commit
2e074a4391
  1. 4
      APP_Framework/Framework/sensor/sensor.c
  2. 1
      APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/include/pthread.h
  3. 2
      Ubiquitous/XiUOS/Makefile
  4. 4
      Ubiquitous/XiUOS/arch/risc-v/Makefile
  5. 3
      Ubiquitous/XiUOS/arch/risc-v/gap8/Makefile
  6. 305
      Ubiquitous/XiUOS/arch/risc-v/gap8/arch_interrupt.h
  7. 381
      Ubiquitous/XiUOS/arch/risc-v/gap8/boot.S
  8. 2064
      Ubiquitous/XiUOS/arch/risc-v/gap8/gap8.h
  9. 209
      Ubiquitous/XiUOS/arch/risc-v/gap8/interrupt.c
  10. 19
      Ubiquitous/XiUOS/arch/risc-v/gap8/tick.c
  11. 69
      Ubiquitous/XiUOS/board/gapuino/Kconfig
  12. 6
      Ubiquitous/XiUOS/board/gapuino/Makefile
  13. 175
      Ubiquitous/XiUOS/board/gapuino/README.md
  14. 59
      Ubiquitous/XiUOS/board/gapuino/board.c
  15. 68
      Ubiquitous/XiUOS/board/gapuino/board.h
  16. 38
      Ubiquitous/XiUOS/board/gapuino/config.mk
  17. BIN
      Ubiquitous/XiUOS/board/gapuino/img/choose_board.png
  18. BIN
      Ubiquitous/XiUOS/board/gapuino/img/gdb_load.png
  19. BIN
      Ubiquitous/XiUOS/board/gapuino/img/menuconfig.png
  20. BIN
      Ubiquitous/XiUOS/board/gapuino/img/openocd.png
  21. BIN
      Ubiquitous/XiUOS/board/gapuino/img/terminal.png
  22. BIN
      Ubiquitous/XiUOS/board/gapuino/img/vscode.jpg
  23. 138
      Ubiquitous/XiUOS/board/gapuino/link.lds
  24. 25
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/Kconfig
  25. 21
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/Makefile
  26. 11
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/gpio/Kconfig
  27. 3
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/gpio/Makefile
  28. 218
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/gpio/hardware_gpio.c
  29. 38
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/include/connect_uart.h
  30. 75
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/include/gap8_fll.h
  31. 87
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/include/gap8_tim.h
  32. 70
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/include/gap8_uart.h
  33. 305
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/include/hardware_gpio.h
  34. 234
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/include/hardware_udma.h
  35. 1
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/sys_clock/Kconfig
  36. 3
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/sys_clock/Makefile
  37. 147
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/sys_clock/gap8_fll.c
  38. 138
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/sys_clock/gapuino_sysinit.c
  39. 19
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/timer/Kconfig
  40. 3
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/timer/Makefile
  41. 135
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/timer/hardware_hwtimer.c
  42. 14
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/uart/Kconfig
  43. 4
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/uart/Makefile
  44. 329
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/uart/connect_uart.c
  45. 394
      Ubiquitous/XiUOS/board/gapuino/third_party_driver/uart/hardware_udma.c
  46. 10
      Ubiquitous/XiUOS/path_kernel.mk

4
APP_Framework/Framework/sensor/sensor.c

@ -27,10 +27,10 @@ static DoublelistType quant_table[SENSOR_QUANTITY_END];
static DoublelistType sensor_device_list;
/* Sensor quantity list lock */
static int quant_table_lock;
static pthread_mutex_t quant_table_lock;
/* Sensor device list lock */
static int sensor_device_list_lock;
static pthread_mutex_t sensor_device_list_lock;
/**
* @description: Init perception framework

1
APP_Framework/Framework/transform_layer/xiuos/user_api/posix_support/include/pthread.h

@ -61,6 +61,7 @@ extern "C" {
// };
typedef int pid_t;
// typedef int pthread_mutex_t ;
/* function in pthread.c */
int pthread_atfork(void (*prepare)(void), void (*parent)(void), void (*child)(void));

2
Ubiquitous/XiUOS/Makefile

@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
.PHONY:COMPILE_APP COMPILE_KERNEL
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator ok1052-c
support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator ok1052-c gapuino
SRC_DIR:=
export BOARD ?=kd233

4
Ubiquitous/XiUOS/arch/risc-v/Makefile

@ -16,4 +16,8 @@ ifeq ($(CONFIG_BOARD_AIIT_RISCV_EVB),y)
SRC_DIR +=k210
endif
ifeq ($(CONFIG_BOARD_GAPUINO),y)
SRC_DIR +=gap8
endif
include $(KERNEL_ROOT)/compiler.mk

3
Ubiquitous/XiUOS/arch/risc-v/gap8/Makefile

@ -0,0 +1,3 @@
SRC_FILES := boot.S interrupt.c tick.c
include $(KERNEL_ROOT)/compiler.mk

305
Ubiquitous/XiUOS/arch/risc-v/gap8/arch_interrupt.h

@ -0,0 +1,305 @@
/****************************************************************************
* arch/risc-v/include/gap8/irq.h
* GAP8 event system
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals
* have unique ID, which are dispatched to the FC or cluster by the SOC
* event unit, and then by the FC event unit or cluster event unit, and
* finally to FC or cluster. Peripherals share the same IRQ entry.
****************************************************************************/
/**
* @file arch_interrupt.h
* @brief support gap8 interrupt
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-09-02
*/
/*************************************************
File name: arch_interrupt.h
Description: support gap8 interrupt
Others: take nuttx/arch/risc-v/include/gap8/irq.h for references
https://github.com/apache/incubator-nuttx.git
History:
1. Date: 2021-09-02
Author: AIIT XUOS Lab
Modification: add interrupt function definition
*************************************************/
#ifndef ARCH_INTERRUPT_H__
#define ARCH_INTERRUPT_H__
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Unique ID in SOC domain */
/* uDMA data events.
* Each peripheral has a uDMA_ID.
* Each peripheral also has RX and TX event ID, which happen to be 2*uDMA_ID
* and 2*uDMA_ID+1.
*/
#define GAP8_EVENT_UDMA_LVDS_RX 0
#define GAP8_EVENT_UDMA_LVDS_TX 1
#define GAP8_EVENT_UDMA_SPIM0_RX 2
#define GAP8_EVENT_UDMA_SPIM0_TX 3
#define GAP8_EVENT_UDMA_SPIM1_RX 4
#define GAP8_EVENT_UDMA_SPIM1_TX 5
#define GAP8_EVENT_UDMA_HYPERBUS_RX 6
#define GAP8_EVENT_UDMA_HYPERBUS_TX 7
#define GAP8_EVENT_UDMA_UART_RX 8
#define GAP8_EVENT_UDMA_UART_TX 9
#define GAP8_EVENT_UDMA_I2C0_RX 10
#define GAP8_EVENT_UDMA_I2C0_TX 11
#define GAP8_EVENT_UDMA_I2C1_RX 12
#define GAP8_EVENT_UDMA_I2C1_TX 13
#define GAP8_EVENT_UDMA_TCDM_RX 14
#define GAP8_EVENT_UDMA_TCDM_TX 15
#define GAP8_EVENT_UDMA_SAI_CH0 16
#define GAP8_EVENT_UDMA_SAI_CH1 17
#define GAP8_EVENT_UDMA_CPI_RX 18
#define GAP8_UDMA_MAX_EVENT 18
/* Other events of uDMA peripherals */
#define GAP8_EVENT_LVDS_GEN0 20
#define GAP8_EVENT_LVDS_GEN1 21
#define GAP8_EVENT_SPIM0_EOT 22
#define GAP8_EVENT_SPIM1_EOT 23
#define GAP8_EVENT_HYPERBUS_RESERVED 24
#define GAP8_EVENT_UART_RESERVED 25
#define GAP8_EVENT_I2C0_ERROR 26
#define GAP8_EVENT_I2C1_ERROR 27
#define GAP8_EVENT_I2S_RESERVED 28
#define GAP8_EVENT_CAM_RESERVED 29
/* PMU events */
#define GAP8_EVENT_PMU_CLUSTER_POWER_ON 31
#define GAP8_EVENT_PMU_CLUSTER_RESERVED0 32
#define GAP8_EVENT_PMU_CLUSTER_RESERVED1 33
#define GAP8_EVENT_PMU_CLUSTER_RESERVED2 34
#define GAP8_EVENT_PMU_CLUSTER_CLOCK_GATING 35
#define GAP8_EVENT_PMU_DLC_BRIDGE_PICL_OK 36
#define GAP8_EVENT_PMU_DLC_BRIDGE_SCU_OK 37
/* Other SOC domain peripheral events */
#define GAP8_EVENT_PWM0 38
#define GAP8_EVENT_PWM1 39
#define GAP8_EVENT_PWM2 40
#define GAP8_EVENT_PWM3 41
#define GAP8_EVENT_GPIO 42 /* GPIO group interrupt */
#define GAP8_EVENT_RTC_APB 43
#define GAP8_EVENT_RTC 44
#define GAP8_EVENT_RESERVED0 45
#define GAP8_EVENT_RESERVED1 46
#define GAP8_EVENT_RESERVED2 47
#define GAP8_EVENT_SOC_SW_0 48 /* GAP8 SOC SW Event0 */
#define GAP8_EVENT_SOC_SW_1 49 /* GAP8 SOC SW Event1 */
#define GAP8_EVENT_SOC_SW_2 50 /* GAP8 SOC SW Event2 */
#define GAP8_EVENT_SOC_SW_3 51 /* GAP8 SOC SW Event3 */
#define GAP8_EVENT_SOC_SW_4 52 /* GAP8 SOC SW Event4 */
#define GAP8_EVENT_SOC_SW_5 53 /* GAP8 SOC SW Event5 */
#define GAP8_EVENT_SOC_SW_6 54 /* GAP8 SOC SW Event6 */
#define GAP8_EVENT_SOC_SW_7 55 /* GAP8 SOC SW Event7 */
#define GAP8_EVENT_REF32K_CLK_RISE 56 /* Reference 32K Clock event */
/* FC domain IRQ ID */
#define GAP8_IRQ_FC_SW_0 0
#define GAP8_IRQ_FC_SW_1 1
#define GAP8_IRQ_FC_SW_2 2
#define GAP8_IRQ_FC_SW_3 3
#define GAP8_IRQ_FC_SW_4 4
#define GAP8_IRQ_FC_SW_5 5
#define GAP8_IRQ_FC_SW_6 6
#define GAP8_IRQ_FC_SW_7 7
#define GAP8_IRQ_FC_TIMER_LO 10
#define GAP8_IRQ_FC_TIMER_HI 11
#define GAP8_IRQ_FC_UDMA 27
#define GAP8_IRQ_FC_MPU 28
#define GAP8_IRQ_FC_UDMA_ERR 29
#define GAP8_IRQ_FC_HP_0 30
#define GAP8_IRQ_FC_HP_1 31
#define GAP8_IRQ_RESERVED 60
/* Cluster domain IRQ ID */
/* TODO */
/* RISCY core exception vectors */
#define GAP8_IRQ_RST 32
#define GAP8_IRQ_ILLEGAL 33
#define GAP8_IRQ_SYSCALL 34
/* Total number of IRQs.
* 32 ISRs + reset-handler + illegal-instruction-handler +
* system-call-handler
*/
#define NR_IRQS 35
/****************************************************************************
* Public Types
****************************************************************************/
/* SOC_EU - SOC domain event unit */
typedef struct
{
volatile uint32_t EVENT; /* event register */
volatile uint32_t FC_MASK_MSB; /* fc mask MSB register */
volatile uint32_t FC_MASK_LSB; /* fc mask LSB register */
volatile uint32_t CL_MASK_MSB; /* cluster mask MSB register */
volatile uint32_t CL_MASK_LSB; /* cluster mask LSB register */
volatile uint32_t PR_MASK_MSB; /* propagate mask MSB register */
volatile uint32_t PR_MASK_LSB; /* propagate mask LSB register */
volatile uint32_t ERR_MASK_MSB; /* error mask MSB register */
volatile uint32_t ERR_MASK_LSB; /* error mask LSB register */
volatile uint32_t TIMER_SEL_HI; /* timer high register */
volatile uint32_t TIMER_SEL_LO; /* timer low register */
} soc_eu_reg_t;
#define SOC_EU ((soc_eu_reg_t *)0x1A106000U)
/* FCEU - FC domain event unit */
typedef struct
{
volatile uint32_t MASK; /* mask register */
volatile uint32_t MASK_AND; /* mask-and(clr) register */
volatile uint32_t MASK_OR; /* mask-or(set) register */
volatile uint32_t MASK_IRQ; /* irq mask register */
volatile uint32_t MASK_IRQ_AND; /* irq mask-and(clr) register */
volatile uint32_t MASK_IRQ_OR; /* irq mask-or(set) register */
volatile uint32_t STATUS; /* clock Status register */
volatile uint32_t BUFFER; /* irq pending register */
volatile uint32_t BUFFER_MASKED; /* buffer masked register */
volatile uint32_t BUFFER_IRQ_MASKED; /* buffer irq masked register */
volatile uint32_t BUFFER_CLEAR; /* clear irq pending */
volatile uint32_t SW_EVENTS_MASK; /* software event mask register */
volatile uint32_t SW_EVENTS_MASK_AND; /* software event mask and register */
volatile uint32_t SW_EVENTS_MASK_OR; /* software event mask or register */
volatile uint32_t EVENT_WAIT; /* event wait register */
volatile uint32_t EVENT_WAIT_CLEAR; /* event wait clear register */
volatile uint32_t MASK_SEC_IRQ; /* mask sec irq register */
} fceu_reg_t;
#define FCEU ((fceu_reg_t*)0x00204000U)
/* Current interrupt event ID */
typedef struct
{
volatile uint32_t CURRENT_EVENT; /* current event register */
} soc_event_reg_t;
#define SOC_EVENTS ((soc_event_reg_t*)0x00200F00UL)
/* event trigger and mask */
typedef struct
{
volatile uint32_t TRIGGER_SET[8]; /* trigger set register */
volatile uint32_t _reserved0[8]; /* Offset: 0x20 (R/W) Empty Registers */
volatile uint32_t TRIGGER_WAIT[8]; /* trigger wait register */
volatile uint32_t _reserved1[8]; /* Offset: 0x60 (R/W) Empty Registers */
volatile uint32_t TRIGGER_CLR[8]; /* trigger clear register */
} eu_sw_events_trigger_reg_t;
#define EU_SW_EVNT_TRIG ((eu_sw_events_trigger_reg_t*)0x00204100UL)
#define ARCH_MAX_IRQ_NUM NR_IRQS
int ArchEnableHwIrq(uint32_t irq_num);
int ArchDisableHwIrq(uint32_t irq_num);
/****************************************************************************
* Name: up_disable_event
*
* Description:
* Disable the specific event. Note that setting 1 means to disable an
* event...
*
****************************************************************************/
static inline void up_disable_event(int event)
{
if (event >= 32)
{
SOC_EU->FC_MASK_MSB |= (1 << (event - 32));
}
else
{
SOC_EU->FC_MASK_LSB |= (1 << event);
}
}
/****************************************************************************
* Name: up_enable_event
*
* Description:
* Enable the specific event. Note that setting 0 means to enable an
* event...
*
****************************************************************************/
static inline void up_enable_event(int event)
{
if (event >= 32)
{
SOC_EU->FC_MASK_MSB &= ~(1 << (event - 32));
}
else
{
SOC_EU->FC_MASK_LSB &= ~(1 << event);
}
}
#endif

381
Ubiquitous/XiUOS/arch/risc-v/gap8/boot.S

@ -0,0 +1,381 @@
/****************************************************************************
* arch/risc-v/src/gapuino/gap8_head.S
* Startup file for FC of GAP8
* Interrupt vector and reset handler
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/**
* @file boot.s
* @brief support gap8 interrupt and startup
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-09-02
*/
/*************************************************
File name: boot.s
Description: support gap8 interrupt and startup
Others: take nuttx/arch/risc-v/gap8/gap8_head.S for references
https://github.com/apache/incubator-nuttx.git
History:
1. Date: 2021-09-02
Author: AIIT XUOS Lab
Modification: modify startup sequence and interrupt process
*************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Exception context size: EPC + 31 common regs + 6 loop regs */
#include "boot.h"
#define EXCEPTION_STACK_SIZE 4*38
/****************************************************************************
* Assembler Macro Definitions
****************************************************************************/
/* save all the registers on interrupt entry */
.macro SAVE_REGS
addi sp, sp, -EXCEPTION_STACK_SIZE
sw x1, 1*4(sp) /* ra */
sw x3, 3*4(sp) /* gp */
sw x4, 4*4(sp) /* tp */
sw x5, 5*4(sp) /* t0 */
sw x6, 6*4(sp) /* t1 */
sw x7, 7*4(sp) /* t2 */
sw x8, 8*4(sp) /* s0 */
sw x9, 9*4(sp) /* s1 */
sw x10, 10*4(sp) /* a0 */
sw x11, 11*4(sp) /* a1 */
sw x12, 12*4(sp) /* a2 */
sw x13, 13*4(sp) /* a3 */
sw x14, 14*4(sp) /* a4 */
sw x15, 15*4(sp) /* a5 */
sw x16, 16*4(sp) /* a6 */
sw x17, 17*4(sp) /* a7 */
sw x18, 18*4(sp) /* s2 */
sw x19, 19*4(sp) /* s3 */
sw x20, 20*4(sp) /* s4 */
sw x21, 21*4(sp) /* s5 */
sw x22, 22*4(sp) /* s6 */
sw x23, 23*4(sp) /* s7 */
sw x24, 24*4(sp) /* s8 */
sw x25, 25*4(sp) /* s9 */
sw x26, 26*4(sp) /* s10 */
sw x27, 27*4(sp) /* s11 */
sw x28, 28*4(sp) /* t3 */
sw x29, 29*4(sp) /* t4 */
sw x30, 30*4(sp) /* t5 */
sw x31, 31*4(sp) /* t6 */
csrr x28, 0x7B0
csrr x29, 0x7B1
csrr x30, 0x7B2
sw x28, 32*4(sp) /* lpstart[0] */
sw x29, 33*4(sp) /* lpend[0] */
sw x30, 34*4(sp) /* lpcount[0] */
csrr x28, 0x7B4
csrr x29, 0x7B5
csrr x30, 0x7B6
sw x28, 35*4(sp) /* lpstart[1] */
sw x29, 36*4(sp) /* lpend[1] */
sw x30, 37*4(sp) /* lpcount[1] */
addi s0, sp, EXCEPTION_STACK_SIZE
sw s0, 2*4(sp) /* original SP */
.endm
/* restore regs and `mret` */
.macro RESTORE_REGS
lw x28, 35*4(sp) /* lpstart[1] */
lw x29, 36*4(sp) /* lpend[1] */
lw x30, 37*4(sp) /* lpcount[1] */
csrrw x0, 0x7B4, x28
csrrw x0, 0x7B5, x29
csrrw x0, 0x7B6, x30
lw x28, 32*4(sp) /* lpstart[0] */
lw x29, 33*4(sp) /* lpend[0] */
lw x30, 34*4(sp) /* lpcount[0] */
csrrw x0, 0x7B0, x28
csrrw x0, 0x7B1, x29
csrrw x0, 0x7B2, x30
li s0, 0x1880 /* machine mode, UPIE & MPIE enabled */
csrrw x0, mstatus, s0
lw x3, 3*4(sp) /* gp */
lw x4, 4*4(sp) /* tp */
lw x5, 5*4(sp) /* t0 */
lw x6, 6*4(sp) /* t1 */
lw x7, 7*4(sp) /* t2 */
lw x8, 8*4(sp) /* s0 */
lw x9, 9*4(sp) /* s1 */
lw x10, 10*4(sp) /* a0 */
lw x11, 11*4(sp) /* a1 */
lw x12, 12*4(sp) /* a2 */
lw x13, 13*4(sp) /* a3 */
lw x14, 14*4(sp) /* a4 */
lw x15, 15*4(sp) /* a5 */
lw x16, 16*4(sp) /* a6 */
lw x17, 17*4(sp) /* a7 */
lw x18, 18*4(sp) /* s2 */
lw x19, 19*4(sp) /* s3 */
lw x20, 20*4(sp) /* s4 */
lw x21, 21*4(sp) /* s5 */
lw x22, 22*4(sp) /* s6 */
lw x23, 23*4(sp) /* s7 */
lw x24, 24*4(sp) /* s8 */
lw x25, 25*4(sp) /* s9 */
lw x26, 26*4(sp) /* s10 */
lw x27, 27*4(sp) /* s11 */
lw x28, 28*4(sp) /* t3 */
lw x29, 29*4(sp) /* t4 */
lw x30, 30*4(sp) /* t5 */
lw x31, 31*4(sp) /* t6 */
lw x1, 1*4(sp) /* ra */
lw sp, 2*4(sp) /* restore original sp */
.endm
.macro WRAP_IRQ Routine, IRQn
wrap_irq_\Routine :
SAVE_X_REGISTERS
mv fp, sp
li a0, \IRQn /* irq = IRQn */
mv a1, sp /* context = sp */
call gap8_dispatch_irq
mv sp, fp
mv a0, fp
call KTaskOsAssignAfterIrq
j SwitchKTaskContextExit
.endm
/*******************************************************************************
* External Variables and Functions
*******************************************************************************/
.extern __bss_start
.extern __bss_end
.extern _idle_stack_end
.extern __data_start__
.extern gap8_dispatch_irq
.extern entry
.extern gapuino_sysinit
.extern GapuinoStart
.globl reset_handler
/*******************************************************************************
* Reset handler
*******************************************************************************/
reset_handler:
#if 0
csrr a0, 0xf14 /* Cluster ID */
andi a1, a0, 0x1f /* Core ID */
srli a0, a0, 5
#endif
# la gp, __data_start__
li a0, 0x1800 /* Set MSTATUS : Machine Mode */
csrw mstatus, a0
li a0, 0x1C000000 /* Set MTVEC */
csrw mtvec, a0
/* Stack initialization */
la x2, _idle_stack_end
/* Clear BSS */
la x26, __bss_start
la x27, __bss_end
bge x26, x27, zero_loop_end
zero_loop:
sw x0, 0(x26)
addi x26, x26, 4
ble x26, x27, zero_loop
zero_loop_end:
csrr a0, 0xf14 /* Cluster ID */
andi a1, a0, 0x1f /* Core ID */
j GapuinoStart
dead_loop:
jal x0, dead_loop
/* IRQ wrappers
* IRQn are identical to gap8_interrupt.h
*/
WRAP_IRQ sw_evt0, 0
WRAP_IRQ sw_evt1, 1
WRAP_IRQ sw_evt2, 2
WRAP_IRQ sw_evt3, 3
WRAP_IRQ sw_evt4, 4
WRAP_IRQ sw_evt5, 5
WRAP_IRQ sw_evt6, 6
WRAP_IRQ sw_evt7, 7
WRAP_IRQ timer_lo, 10
WRAP_IRQ timer_hi, 11
WRAP_IRQ udma, 27
WRAP_IRQ mpu, 28
WRAP_IRQ udma_err, 29
WRAP_IRQ fc_hp0, 30
WRAP_IRQ fc_hp1, 31
WRAP_IRQ reserved, 60
/* RISCV exceptions */
illegal_insn_handler:
csrr s0, mepc
sw s0, 0*4(sp) /* exception PC */
/* Spin here so that debugger would read `s0` */
1:
j 1b
/* Systemcall handler */
ecall_insn_handler:
SAVE_REGS
/* Point to the next instruction of `ecall` */
csrr s0, mepc
addi s0, s0, 4
sw s0, 0(sp) /* exception PC */
li a0, 34 /* irq = 34 */
mv a1, sp /* context = sp */
jal x1, gap8_dispatch_irq
/* If context switch is needed, return
* a new sp
*/
mv sp, a0
lw s0, 0(sp) /* restore ePC */
csrw mepc, s0
RESTORE_REGS
mret
/*******************************************************************************
* INTERRUPT VECTOR TABLE
*******************************************************************************/
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors_M, "ax"
.option norvc;
j wrap_irq_sw_evt0 /* 0 */
j wrap_irq_sw_evt1 /* 1 */
j wrap_irq_sw_evt2 /* 2 */
j wrap_irq_sw_evt3 /* 3 */
j wrap_irq_sw_evt4 /* 4 */
j wrap_irq_sw_evt5 /* 5 */
j wrap_irq_sw_evt6 /* 6 */
j wrap_irq_sw_evt7 /* 7 */
j wrap_irq_reserved /* 8 */
j wrap_irq_reserved /* 9 */
j wrap_irq_timer_lo /* 10 */
j wrap_irq_timer_hi /* 11 */
j wrap_irq_reserved /* 12 */
j wrap_irq_reserved /* 13 */
j wrap_irq_reserved /* 14 */
j wrap_irq_reserved /* 15 */
j wrap_irq_reserved /* 16 */
j wrap_irq_reserved /* 17 */
j wrap_irq_reserved /* 18 */
j wrap_irq_reserved /* 19 */
j wrap_irq_reserved /* 20 */
j wrap_irq_reserved /* 21 */
j wrap_irq_reserved /* 22 */
j wrap_irq_reserved /* 23 */
j wrap_irq_reserved /* 24 */
j wrap_irq_reserved /* 25 */
j wrap_irq_reserved /* 26 */
j wrap_irq_udma /* 27 */
j wrap_irq_mpu /* 28 */
j wrap_irq_udma_err /* 29 */
j wrap_irq_fc_hp0 /* 30 */
j wrap_irq_fc_hp1 /* 31 */
j reset_handler /* 32 */
j illegal_insn_handler/* 33 */
j ecall_insn_handler /* 34 */
/****************************************************************************
* This variable is pointed to the structure containing all information
* exchanged with the platform loader. It is using a fixed address so that
* the loader can also find it and then knows the address of the debug
* structure.
****************************************************************************/
.section .dbg_struct, "ax"
.option norvc;
.org 0x90
.global __rt_debug_struct_ptr
__rt_debug_struct_ptr:
.word Debug_Struct
/****************************************************************************
* This global variable is unsigned int g_idle_topstack and is exported here
* only because of its coupling to idle thread stack.
****************************************************************************/
.section .data
.global g_idle_topstack
g_idle_topstack:
.word _idle_stack_end

2064
Ubiquitous/XiUOS/arch/risc-v/gap8/gap8.h

File diff suppressed because it is too large

209
Ubiquitous/XiUOS/arch/risc-v/gap8/interrupt.c

@ -0,0 +1,209 @@
/****************************************************************************
* arch/risc-v/src/gap8/gap8_interrupt.c
* GAP8 event system
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: hhuysqt <1020988872@qq.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* GAP8 features a FC controller and a 8-core cluster. IRQ from peripherals
* have unique ID, which are dispatched to the FC or cluster by the SOC
* event unit, and then by the FC event unit or cluster event unit, and
* finally to FC or cluster. Peripherals share the same IRQ entry.
****************************************************************************/
/**
* @file interrupt.c
* @brief support gap8 interrupt enable and disable
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-09-02
*/
/*************************************************
File name: interrupt.c
Description: support gap8 interrupt enable and disable
Others: take nuttx/arch/risc-v/gap8/gap8_interrupt.c for references
https://github.com/apache/incubator-nuttx.git
History:
1. Date: 2021-09-02
Author: AIIT XUOS Lab
Modification: modify interrupt enable/disable function and add interrupt process function
*************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch_interrupt.h>
#include <xs_base.h>
#include <xs_isr.h>
/****************************************************************************
* Public Data
****************************************************************************/
volatile uint32_t *g_current_regs;
/****************************************************************************
* Public Functions
****************************************************************************/
/* Function exported to the NuttX kernel */
void up_mdelay(unsigned int time)
{
while (time--)
{
volatile int dummy = 200000;
while (dummy--)
{
}
}
}
/****************************************************************************
* Name: ArchDisableHwIrq
*
* Description:
* Disable the IRQ specified by 'irq'. Mind the Machine privilege.
*
****************************************************************************/
int ArchDisableHwIrq(uint32_t irq_num)
{
FCEU->MASK_IRQ_AND = (1UL << irq_num);
}
/****************************************************************************
* Name: ArchEnableHwIrq
*
* Description:
* Enable the IRQ specified by 'irq'. Mind the Machine privilege.
*
****************************************************************************/
int ArchEnableHwIrq(uint32_t irq_num)
{
FCEU->MASK_IRQ_OR = (1 << irq_num);
}
x_base DisableLocalInterrupt(void)
{
x_base level;
asm volatile("nop");
asm volatile ("csrrci %0, mstatus, 8" : "=r"(level));
return level;
}
/****************************************************************************
* Name: EnableLocalInterrupt
*
* Description:
* Return the current interrupt state and enable interrupts
*
****************************************************************************/
void EnableLocalInterrupt(x_base oldstat)
{
x_base newstat;
asm volatile ("csrw mstatus, %0" :: "r"(oldstat));
}
/****************************************************************************
* Name: gap8_sleep_wait_sw_evnt
*
* Description:
* Sleep on specific event.
*
****************************************************************************/
void gap8_sleep_wait_sw_evnt(uint32_t event_mask)
{
FCEU->MASK_OR = event_mask;
// __builtin_pulp_event_unit_read((void *)&FCEU->EVENT_WAIT_CLEAR, 0);
FCEU->MASK_AND = event_mask;
}
/****************************************************************************
* Name: irqinitialize
*
* Description:
* Initialize the IRQ on FC.
*
****************************************************************************/
extern void gap8_udma_doirq(int irq, void *arg);
void irqinitialize(void)
{
/* Deactivate all the soc events */
SOC_EU->FC_MASK_MSB = 0xffffffff;
SOC_EU->FC_MASK_LSB = 0xffffffff;
/* enable soc peripheral interrupt */
isrManager.done->registerIrq(GAP8_IRQ_FC_UDMA, gap8_udma_doirq, NONE);
isrManager.done->enableIrq(GAP8_IRQ_FC_UDMA);
}
/****************************************************************************
* Name: gap8_dispatch_irq
*
* Description:
* Called from IRQ vectors. Input vector id. Return SP pointer, modified
* or not.
*
****************************************************************************/
void *gap8_dispatch_irq(uint32_t vector, void *current_regs)
{
/* Clear pending bit and trigger a software event.
* GAP8 would sleep on sw event 3 on up_idle().
*/
FCEU->BUFFER_CLEAR = (1 << vector);
EU_SW_EVNT_TRIG->TRIGGER_SET[3] = 0;
g_current_regs = current_regs;
isrManager.done->incCounter();
isrManager.done->handleIrq(vector);
isrManager.done->decCounter();
}

19
Ubiquitous/XiUOS/arch/risc-v/gap8/tick.c

@ -0,0 +1,19 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <xs_ktick.h>
static volatile unsigned long tick_cycles = 0;
int TickIsr(void)
{
TickAndTaskTimesliceUpdate();
return 0;
}

69
Ubiquitous/XiUOS/board/gapuino/Kconfig

@ -0,0 +1,69 @@
mainmenu "XiUOS Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config KERNEL_DIR
string
option env="KERNEL_ROOT"
default "../.."
config BOARD_GAPUINO
bool
select ARCH_RISCV
default y
source "$KERNEL_DIR/arch/Kconfig"
menu "gapuino feature"
source "$BSP_DIR/third_party_driver/Kconfig"
menu "config default board resources"
menu "config board app name"
config BOARD_APP_NAME
string "config board app name"
default "/XiUOS_gapuino_app.bin"
endmenu
menu "config board service table"
config SERVICE_TABLE_ADDRESS
hex "board service table address"
default 0x80100000
endmenu
menu "config hardware resources for connection"
if CONNECTION_COMMUNICATION_ETHERNET
config ETHERNET_UART_NAME
string "ethernet uart name"
default "/dev/uart3_dev3"
endif
if CONNECTION_COMMUNICATION_WIFI
config WIFI_UART_NAME
string "wifi uart name"
default "/dev/uart3_dev3"
endif
endmenu
endmenu
config __STACKSIZE__
int "stack size for interrupt"
default 4096
endmenu
menu "Hardware feature"
source "$KERNEL_DIR/resources/Kconfig"
endmenu
source "$KERNEL_DIR/Kconfig"

6
Ubiquitous/XiUOS/board/gapuino/Makefile

@ -0,0 +1,6 @@
SRC_FILES := board.c
SRC_DIR := third_party_driver
include $(KERNEL_ROOT)/compiler.mk

175
Ubiquitous/XiUOS/board/gapuino/README.md

@ -0,0 +1,175 @@
# 从零开始构建矽璓工业物联操作系统:使用risc-v架构的gapuino 开发板
[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓工业物联操作系统是一款面向工业物联场景的泛在操作系统,来自泛在操作系统研究计划。所谓泛在操作系统(UOS: Ubiquitous Operating Systems),是支持互联网时代人机物融合泛在计算应用模式的新型操作系统,是传统操作系统概念的泛化与延伸。在泛在操作系统技术体系中,不同的泛在计算设备和泛在应用场景需要符合各自特性的不同UOS,XiUOS即是面向工业物联场景的一种UOS,主要由一个极简的微型实时操作系统(RTOS)内核和其上的智能工业物联框架构成,支持工业物联网(IIoT: Industrial Internet of Things)应用。
## 开发环境搭建
### 推荐使用:
**操作系统:** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
**开发工具推荐使用 VSCode ,VScode下载地址为:** VSCode [https://code.visualstudio.com/](https://code.visualstudio.com/),推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
### 依赖包安装:
```
$ sudo apt install build-essential pkg-config
$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev git
```
**源码下载:** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
新建一个空文件夹并进入文件夹中,并下载源码,具体命令如下:
```c
mkdir test && cd test
git clone https://git.trustie.net/xuos/xiuos.git
```
打开源码文件包可以看到以下目录:
| 名称 | 说明 |
| -- | -- |
| application | 应用代码 |
| board | 板级支持包 |
| framework | 应用框架 |
| fs | 文件系统 |
| kernel | 内核源码 |
| resources | 驱动文件 |
| tool | 系统工具 |
使用VScode打开代码,具体操作步骤为:在源码文件夹下打开系统终端,输入`code .`即可打开VScode开发环境,如下图所示:
![vscode](img/vscode.jpg)
### 裁减配置工具的下载
裁减配置工具:
**工具地址:** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)
```c
mkdir kfrontends && cd kfrontends
git clone https://git.trustie.net/xuos/kconfig-frontends.git
```
下载源码后按以下步骤执行软件安装:
```c
cd kconfig-frontends
./xs_build.sh
```
### 编译工具链:
RISC-V: riscv-none-embed-,默认安装到Ubuntu的/opt/,下载源码并解压。[下载网址 http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2](http://101.36.126.201:8011/gnu-mcu-eclipse.tar.bz2)
```shell
$ tar -xjf gnu-mcu-eclipse.tar.bz2 -C /opt/
```
将上述解压的编译工具链的路径添加到board/hifive1-rev-B/config.mk文件当中,例如:
```
export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed-
```
若已存在`export CROSS_COMPILE ?=xxxx` 应该将原有的语句注释,再写入上面的语句。
# 在gapuino board 上创建第一个应用
## 1.gapuino board 简介
| 硬件 | 描述 |
| -- | -- |
|芯片型号| gap8 |
|架构| RV32IMAC |
|主频| 200+MHz |
|片内SRAM| 512KB |
| 外设 | UART、SPI、I2C |
XiUOS板级当前支持使用UART。
## 2. 代码编写与编译说明
编辑环境:`VScode`
编译工具链:`riscv-none-embed-gcc`
使用`VScode`打开工程的方法有多种,本文介绍一种快捷键,在项目目录下将`code .`输入终端即可打开目标项目
修改`applications`文件夹下`main.c`
在输出函数中写入 Hello, world! \n 完成代码编辑。
编译步骤:
1.在VScode终端下执行以下命令,生成配置文件
```
make BOARD=gapuino menuconfig
```
2.在menuconfig界面配置需要关闭和开启的功能,按回车键进入下级菜单,按Y键选中需要开启的功能,按N键选中需要关闭的功能,配置结束后选择Exit保存并退出
![menuconfig](img/menuconfig.png)
3.继续执行以下命令,进行编译
```
make BOARD=gapuino
```
4.如果编译正确无误,build文件夹下会产生XiUOS_gapuino.elf、XiUOS_gapuino.bin文件。
>注:最后可以执行以下命令,清除配置文件和编译生成的文件
```
make BOARD=gapuino distclean
```
## 3. 烧写及执行
gapuino支持jtag,可以通过jtag进行烧录和调试。
调试烧写需要下载gap sdk和openocd,下载配置方法参见以下文档:
https://greenwaves-technologies.com/setting-up-sdk/
在SDK 和openocd安装完成以后,按照如下步骤进行调试:
1、进入sdk目录路径下
```
cd ~/gap_sdk
```
2、在当前终端输入
```
source sourceme.sh
```
出现如下图所示的界面,输入7选择单板名称;
![choose](./img/choose_board.png)
3、先按开发板的复位键,再在当前终端输入
```
gap8-openocd -f interface/ftdi/gapuino_ftdi.cfg -f target/gap8.tcl -f tcl/jtag_boot_entry.tcl
```
在当前终端连接openocd,连接如下图所示:
![openocd](./img/openocd.png)
4、打开一个新的终端,输入以下命令打开终端串口:
```
sudo apt install screen
screen /dev/ttyUSB0 115200
```
5、打开一个新的终端,进入编译生成的elf路径,输入例如:
```
riscv32-unknown-elf-gdb build/XiUOS_gapuino.elf -ex "target remote localhost:3333"
```
结果如下图所示:
![gdb](./img/gdb_load.png)
6、再输入load,最后输入continue命令即可在串口终端看到系统运行界面,如下图所示:
![terminal](./img/terminal.png)

59
Ubiquitous/XiUOS/board/gapuino/board.c

@ -0,0 +1,59 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.c
* @brief support gap8 init configure and start-up
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-09-02
*/
#include <board.h>
#include <arch_interrupt.h>
#include <xiuos.h>
#include <device.h>
extern void entry(void);
extern int InitHwUart(void);
extern void irqinitialize(void);
extern void timer_initialize(void);
extern void gapuino_sysinit(void);
extern unsigned int __bss_end__;
void GapuinoStart(uint32_t mhartid)
{
gapuino_sysinit();
entry();
}
void InitBoardHardware(void)
{
irqinitialize();
InitBoardMemory(MEMORY_START_ADDRESS, MEMORY_END_ADDRESS);
InitHwUart();
InstallConsole("uart0", "uart0_drv", "uart0_dev0");
KPrintf("console init completed.\n");
KPrintf("board initialization......\n");
timer_initialize();
KPrintf("memory address range: [0x%08x - 0x%08x], size: %d\n", (x_ubase) MEMORY_START_ADDRESS, (x_ubase) MEMORY_END_ADDRESS, GAP8_SRAM_SIZE);
/* initialize memory system */
KPrintf("board init done.\n");
KPrintf("start kernel...\n");
return;
}

68
Ubiquitous/XiUOS/board/gapuino/board.h

@ -0,0 +1,68 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file board.h
* @brief define gapuino-board init configure and start-up function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2021-09-02
*/
/*************************************************
File name: board.h
Description: define gapuino-board init configure and start-up function
Others:
History:
1. Date: 2021-09-02
Author: AIIT XUOS Lab
Modification:
1. define gapuino-board InitBoardHardware
2. define gapuino-board data and bss struct
*************************************************/
#ifndef BOARD_H__
#define BOARD_H__
#include <xsconfig.h>
#include <stdint.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
extern unsigned int __bss_start__;
extern unsigned int __bss_end__;
extern unsigned int _end;
extern unsigned int __stack_end__;
extern unsigned int g_service_table_start;
extern unsigned int g_service_table_end;
// #define MEMORY_START_ADDRESS (void*)(&__bss_end__)
#define MEMORY_START_ADDRESS (void*)(&_end)
#define GAP8_SRAM_SIZE 512
#define MEMORY_END_ADDRESS (void*)(0x1C000000 + GAP8_SRAM_SIZE * 1024)
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif
#endif

38
Ubiquitous/XiUOS/board/gapuino/config.mk

@ -0,0 +1,38 @@
# ARCHCFLAGS = -fno-builtin
# ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
# ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
# ARCHOPTIMIZATION = -g
# ASARCHCPUFLAGS += -Wa,-g
# ARCHCPUFLAGS = -march=rv32imcxgap8 -mPE=8 -mFC=1 -D__riscv__ -D__pulp__ -D__GAP8__ -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields
# export CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) -O0 -g3 -gdwarf-2
# export AFLAGS := $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS)
# export LFLAGS := -march=rv32imcxgap8 -mPE=8 -mFC=1 -nostartfiles -Wl,--gc-sections,-Map=XiUOS_gap8.map,-cref,-u,reset_handler -T $(BSP_ROOT)/link.lds
# export APPLFLAGS := -march=rv32imcxgap8 -mPE=8 -mFC=1 -nostartfiles -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
# export CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS)
# export CROSS_COMPILE ?=/opt/gap_riscv_toolchain/bin/riscv32-unknown-elf-
export CFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -fgnu89-inline -Werror
export AFLAGS := -c -mcmodel=medany -march=rv32imac -mabi=ilp32 -x assembler-with-cpp -ggdb
export LFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiUOS_gap8.map,-cref,-u,_start -T $(BSP_ROOT)/link.lds
export APPLFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -nostartfiles -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
export CXXFLAGS := -mcmodel=medany -march=rv32imac -mabi=ilp32 -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -O0 -ggdb -Werror
export CROSS_COMPILE ?=/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin/riscv-none-embed-
export DEFINES := -DHAVE_CCONFIG_H -DHAVE_SIGINFO
export ARCH = risc-v
export MCU = GAP8

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Ubiquitous/XiUOS/board/gapuino/link.lds

@ -0,0 +1,138 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
OUTPUT_ARCH( riscv )
SEARCH_DIR(.)
__DYNAMIC = 0;
MEMORY
{
L2 (wxa!ri) : ORIGIN = 0x1C000000, LENGTH = 0x80000
FC_tcdm : ORIGIN = 0x1B000004, LENGTH = 0x3ffc
FC_tcdm_aliased : ORIGIN = 0x00000004, LENGTH = 0x3ffc
}
__L1_STACK_SIZE = 0x400;
__FC_STACK_SIZE = 4096;
/* We have to align each sector to word boundaries as our current s19->slm
* conversion scripts are not able to handle non-word aligned sections.
*/
ENTRY( reset_handler )
SECTIONS
{
.vectors_M :
{
. = ALIGN(4);
IRQ_U_Vector_Base = .;
KEEP(*(.vectors_M))
} > L2
.dbg_struct :
{
. = ALIGN(4);
IRQ_M_Vector_Base = .;
KEEP(*(.dbg_struct))
} > L2
. = ALIGN(4);
.text : {
PROVIDE( _text = ABSOLUTE(.) );
/* _stext = .; */
*(.text .text.*)
/* *(.rodata .rodata*) */
/* _etext = .; */
/* section information for shell */
. = ALIGN(4);
_shell_command_start = .;
KEEP (*(shellCommand))
_shell_command_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
__isrtbl_idx_start = .;
KEEP(*(.isrtbl.idx))
__isrtbl_start = .;
KEEP(*(.isrtbl))
__isrtbl_end = .;
. = ALIGN(4);
PROVIDE(g_service_table_start = ABSOLUTE(.));
KEEP(*(.g_service_table))