Merge branch 'master' of https://git.trustie.net/IACU/xiuos into spi_flash_test

Makefile

@@ -5,7 +5,7 @@ MAKEFLAGS += --no-print-directory
 .PHONY:COMPILE_APP COMPILE_KERNEL
 
 
-support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator
+support :=kd233 stm32f407-st-discovery maix-go stm32f407zgt6 aiit-riscv64-board aiit-arm32-board hifive1-rev-B hifive1-emulator k210-emulator cortex-m3-emulator
 SRC_DIR:=
 
 export BOARD ?=kd233

arch/arm/Makefile

@@ -1,4 +1,12 @@
 #公共部分
-SRC_DIR := shared cortex-m4  
+SRC_DIR := shared
+
+ifeq ($(CONFIG_BOARD_CORTEX_M3_EVB),y)
+SRC_DIR +=cortex-m3
+endif
+
+ifeq ($(CONFIG_BOARD_STM32F407_EVB),y)
+SRC_DIR +=cortex-m4
+endif
 
 include $(KERNEL_ROOT)/compiler.mk

arch/arm/cortex-m3/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := boot.c  interrupt.c interrupt_vector.S
+
+include $(KERNEL_ROOT)/compiler.mk

arch/arm/cortex-m3/arch_interrupt.h

@@ -0,0 +1,28 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+#ifndef ARCH_INTERRUPT_H__
+#define ARCH_INTERRUPT_H__
+
+#include <xs_base.h>
+
+#define ARCH_MAX_IRQ_NUM (256)
+
+#define ARCH_IRQ_NUM_OFFSET 0
+
+#define SYSTICK_IRQN       15
+#define UART1_IRQn         21
+
+int32 ArchEnableHwIrq(uint32 irq_num);
+int32 ArchDisableHwIrq(uint32 irq_num);
+
+#endif

arch/arm/cortex-m3/boot.c

@@ -0,0 +1,97 @@
+//*****************************************************************************
+//
+// startup_gcc.c - Startup code for use with GNU tools.
+//
+// Copyright (c) 2013 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 10636 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+/**
+* @file boot.c
+* @brief derived from Stellaris Firmware Development Package
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-13
+*/
+
+/*************************************************
+File name: boot.c
+Description: Reset and init function
+Others: 
+History: 
+1. Date: 2021-05-13
+Author: AIIT XUOS Lab
+Modification: 
+1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package   for XiUOS
+*************************************************/
+
+extern unsigned long _sidata;
+extern unsigned long _sdata;
+extern unsigned long _edata;
+extern unsigned long _sbss;
+extern unsigned long _ebss;
+extern int entry(void);
+
+void
+Reset_Handler(void)
+{
+    unsigned long *pulSrc, *pulDest;
+
+    //
+    // Copy the data segment initializers from flash to SRAM.
+    //
+    pulSrc = &_sidata;
+    for(pulDest = &_sdata; pulDest < &_edata; )
+    {
+        *pulDest++ = *pulSrc++;
+    }
+
+    //
+    // Zero fill the bss segment.
+    //
+    __asm("    ldr     r0, =_sbss\n"
+          "    ldr     r1, =_ebss\n"
+          "    mov     r2, #0\n"
+          "    .thumb_func\n"
+          "zero_loop:\n"
+          "        cmp     r0, r1\n"
+          "        it      lt\n"
+          "        strlt   r2, [r0], #4\n"
+          "        blt     zero_loop");
+
+    //
+    // Call the application's entry point.
+    //
+    entry();
+}

arch/arm/cortex-m3/interrupt.c

@@ -0,0 +1,84 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file interrupt.c
+* @brief support arm cortex-m4 interrupt function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-04-29
+*/
+
+#include <xs_base.h>
+#include <xs_isr.h>
+
+
+x_base __attribute__((naked)) DisableLocalInterrupt()
+{
+    asm volatile ("MRS     r0, PRIMASK");
+    asm volatile ("CPSID   I");
+    asm volatile ("BX      LR ");
+}
+
+void __attribute__((naked)) EnableLocalInterrupt(x_base level)
+{
+    asm volatile ("MSR     PRIMASK, r0");
+    asm volatile ("BX      LR");
+}
+
+int32 ArchEnableHwIrq(uint32 irq_num)
+{
+    return EOK;
+}
+
+int32 ArchDisableHwIrq(uint32 irq_num)
+{
+    return EOK;
+}
+
+extern  void KTaskOsAssignAfterIrq(void *context);
+
+void IsrEntry()
+{
+    uint32 ipsr;
+
+    __asm__ volatile("MRS %0, IPSR" : "=r"(ipsr));
+
+    isrManager.done->incCounter();
+    isrManager.done->handleIrq(ipsr);
+    KTaskOsAssignAfterIrq(NONE);
+    isrManager.done->decCounter();
+    
+}
+
+void UsageFault_Handler(int irqn, void *arg)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+void BusFault_Handler(int irqn, void *arg)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+void NMI_Handler(int irqn, void *arg)
+{
+    while (1)
+  {
+  }
+}

arch/arm/cortex-m3/interrupt_vector.S

@@ -0,0 +1,138 @@
+//*****************************************************************************
+//
+// startup_gcc.c - Startup code for use with GNU tools.
+//
+// Copyright (c) 2013 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 10636 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+/**
+* @file interrupt_vector.S
+* @brief derived from Stellaris Firmware Development Package
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-13
+*/
+
+/*************************************************
+File name: interrupt_vector.S
+Description: vector table for a Cortex M3
+Others: 
+History: 
+1. Date: 2021-05-13
+Author: AIIT XUOS Lab
+Modification: 
+1. take startup_gcc.c from revision 10636 of the Stellaris Firmware Development Package   for XiUOS
+*************************************************/
+
+
+//*****************************************************************************
+//
+// The vector table.  Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+//*****************************************************************************
+.globl  InterruptVectors
+
+/******************************************************************************
+*******************************************************************************/
+  .section  .isr_vector,"a",%progbits
+  .type  InterruptVectors, %object
+  .size  InterruptVectors, .-InterruptVectors
+
+InterruptVectors:
+  .word  _sp
+  .word  Reset_Handler
+  .word  NMI_Handler                     //NMI_Handler
+  .word  HardFaultHandler
+  .word  MemFaultHandler                     //MemManage_Handler
+  .word  BusFault_Handler                     //BusFault_Handler
+  .word  UsageFault_Handler                     //UsageFault_Handler
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry
+  .word  IsrEntry                     //SVC_Handler
+  .word  IsrEntry                     //DebugMon_Handler
+  .word  IsrEntry
+  .word  PendSV_Handler
+  .word  IsrEntry                     //systick 
+  .word  IsrEntry                     // GPIO Port A              
+  .word  IsrEntry                     // GPIO Port B              
+  .word  IsrEntry                     // GPIO Port C              
+  .word  IsrEntry                     // GPIO Port D              
+  .word  IsrEntry                     // GPIO Port E              
+  .word  IsrEntry                      // UART0 Rx and Tx  
+  .word  IsrEntry                     // UART1 Rx and Tx          
+  .word  IsrEntry                     // SSI Rx and Tx            
+  .word  IsrEntry                     // I2C Master and Slave     
+  .word  IsrEntry                     // PWM Fault                
+  .word  IsrEntry                     // PWM Generator 0          
+  .word  IsrEntry                     // PWM Generator 1          
+  .word  IsrEntry                     // PWM Generator 2          
+  .word  IsrEntry                     // Quadrature Encoder       
+  .word  IsrEntry                     // ADC Sequence 0           
+  .word  IsrEntry                     // ADC Sequence 1           
+  .word  IsrEntry                     // ADC Sequence 2           
+  .word  IsrEntry                     // ADC Sequence 3           
+  .word  IsrEntry                     // Watchdog timer           
+  .word  IsrEntry                     // Timer 0 subtimer A       
+  .word  IsrEntry                     // Timer 0 subtimer B       
+  .word  IsrEntry                     // Timer 1 subtimer A       
+  .word  IsrEntry                     // Timer 1 subtimer B       
+  .word  IsrEntry                     // Timer 2 subtimer A       
+  .word  IsrEntry                     // Timer 2 subtimer B       
+  .word  IsrEntry                     // Analog Comparator 0      
+  .word  IsrEntry                     // Analog Comparator 1      
+  .word  IsrEntry                     // Analog Comparator 2      
+  .word  IsrEntry                     // System Control (PLL, OSC,
+  .word  IsrEntry                     // FLASH Control            
+  .word  IsrEntry                     // GPIO Port F              
+  .word  IsrEntry                     // GPIO Port G              
+  .word  IsrEntry                     // GPIO Port H              
+  .word  IsrEntry                     // UART2 Rx and Tx          
+  .word  IsrEntry                     // SSI1 Rx and Tx           
+  .word  IsrEntry                     // Timer 3 subtimer A       
+  .word  IsrEntry                     // Timer 3 subtimer B       
+  .word  IsrEntry                     // I2C1 Master and Slave    
+  .word  IsrEntry                     // Quadrature Encoder 1     
+  .word  IsrEntry                     // CAN0                     
+  .word  IsrEntry                     // CAN1                     
+  .word  IsrEntry                     // CAN2                     
+  .word  IsrEntry                            // Ethernet              
+  .word  IsrEntry                     // Hibernate                
+  .word  IsrEntry                     // USB0                     
+  .word  IsrEntry                     // PWM Generator 3          
+  .word  IsrEntry                     // uDMA Software Transfer   
+  .word  IsrEntry                       // uDMA Error               

arch/arm/shared/prepare_ahwstack.c

@@ -14,7 +14,6 @@
 #include <xs_ktask.h>
 #include <xs_assign.h>
 #include "svc_handle.h"
-#include "stm32f4xx.h"
 #include <board.h>
 #include <shell.h>
 
@@ -380,12 +379,6 @@ void MemFaultExceptionPrint(struct ExceptionInfo *ExceptionInfo)
     if ((ExceptionInfo->ExcReturn & 0x10) == 0)
         KPrintf("FPU active!\r\n");
 
-    KPrintf("CFSR: 0x%08x \n", (*((volatile unsigned long *)(SCB->CFSR))) );
-    KPrintf("HFSR: 0x%08x \n",  (*((volatile unsigned long *)(SCB->HFSR))) );
-    KPrintf("DFSR: 0x%08x \n",(*((volatile unsigned long *)(SCB->DFSR))) );
-    KPrintf("MMFAR: 0x%08x \n",(*((volatile unsigned long *)(SCB->MMFAR))));
-    KPrintf("BFAR: 0x%08x \n",(*((volatile unsigned long *)(SCB->BFAR))));
-    KPrintf("AFSR: 0x%08x \n",(*((volatile unsigned long *)(SCB->AFSR))));
 
 #ifdef TOOL_SHELL
     HardFaultTrack();

arch/risc-v/k210/boot.S

@@ -70,13 +70,13 @@ _begin:
   j    Kd233Start
 
 
-#ifdef ARCH_SMP
+
 .data
 .globl cpu2_boot_flag
 .align 3
 cpu2_boot_flag:
     .8byte 0
-#endif
+
 
 .section      .text.entry
 .align 2

board/aiit-riscv64-board/board.c

@@ -84,14 +84,17 @@ void Kd233Start(uint32_t mhartid)
 			/*kernel start entry*/
     		entry();
 			break;
-#ifdef ARCH_SMP
 		case CPU1:
 			while(0x2018050420191010 != cpu2_boot_flag) { ///< waiting for boot flag ,then start cpu1 core
-				
+#ifndef ARCH_SMP
+				asm volatile("wfi");
+#endif
 			}
+#ifdef ARCH_SMP
 			SecondaryCpuCStart();
-			break;
 #endif
+			break;
+
 		default:
 			break;
 	}

board/cortex-m3-emulator/.defconfig

@@ -0,0 +1,248 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# XiUOS Project Configuration
+#
+CONFIG_BOARD_CORTEX_M3_EVB=y
+CONFIG_KERNEL_CONSOLE_DEVICE_NAME="uart0"
+#CONFIG_LED0=24
+#CONFIG_LED1=25
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV32=y
+CONFIG_ARCH_CPU_32BIT=y
+
+#
+# cortex-m3-emulator feature
+#
+# CONFIG_BSP_USING_AUDIO is not set
+# CONFIG_BSP_USING_CAMERA is not set
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_DMA is not set 
+CONFIG_BSP_USING_GPIO=y
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_I2S is not set
+# CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SECURITY is not set
+# CONFIG_BSP_USING_SPI is not set
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART_HS is not set
+# CONFIG_BSP_USING_VIDEO is not set
+# CONFIG_BSP_USING_WDT is not set
+
+#
+# General Purpose UARTs
+#
+
+CONFIG___STACKSIZE__=4096
+
+#
+# Hardware feature
+#
+CONFIG_RESOURCES_SERIAL=y
+# CONFIG_SERIAL_USING_DMA=y
+CONFIG_SERIAL_RB_BUFSZ=64
+CONFIG_FS_VFS=n
+# CONFIG_RESOURCES_HWTIMER is not set
+# CONFIG_RESOURCES_I2C is not set
+# CONFIG_RESOURCES_LCD is not set
+# CONFIG_RESOURCES_SDIO is not set
+# CONFIG_RESOURCES_TOUCH is not set
+# CONFIG_RESOURCES_PIN=y
+# CONFIG_RESOURCES_RTC is not set
+# CONFIG_RESOURCES_SPI is not set
+#CONFIG_RESOURCES_SPI_SD is not set
+#CONFIG_RESOURCES_SPI_SFUD is not set
+# SFUD_USING_SFDP is not set
+# SFUD_USING_FLASH_INFO_TABLE is not set
+# SFUD_DEBUG_LOG is not set
+# CONFIG_RESOURCES_WDT is not set
+# CONFIG_RESOURCES_USB is not set
+# CONFIG_RESOURCES_USB_HOST is not set
+# CONFIG_UDISK_MOUNTPOINT is not set
+# CONFIG_USBH_MSTORAGE is not set
+# CONFIG_RESOURCES_USB_DEVICE is not set
+# CONFIG_USBD_THREAD_STACK_SZ is not set
+
+#
+# Kernel feature
+#
+
+#
+# Kernel Device Object
+#
+CONFIG_KERNEL_DEVICE=y
+CONFIG_KERNEL_CONSOLE=y
+CONFIG_KERNEL_CONSOLEBUF_SIZE=128
+
+#
+# Task feature
+#
+CONFIG_SCHED_POLICY_RR_REMAINSLICE=y
+# CONFIG_SCHED_POLICY_RR is not set
+# CONFIG_SCHED_POLICY_FIFO is not set
+
+#
+# Memory Management
+#
+# CONFIG_KERNEL_MEMBLOCK is not set
+CONFIG_MEM_ALIGN_SIZE=4
+CONFIG_MM_PAGE_SIZE=1024
+
+#
+# Using small memory allocator
+#
+CONFIG_KERNEL_SMALL_MEM_ALLOC=y
+CONFIG_SMALL_NUMBER_32B=32
+CONFIG_SMALL_NUMBER_64B=16
+
+#
+# Inter-Task communication
+#
+# CONFIG_KERNEL_SEMAPHORE=y
+# CONFIG_KERNEL_MUTEX=y
+CONFIG_KERNEL_EVENT=n
+CONFIG_KERNEL_MESSAGEQUEUE=n
+CONFIG_KTASK_PRIORITY_8=y
+CONFIG_KTASK_PRIORITY_MAX=8
+CONFIG_TICK_PER_SECOND=100
+# CONFIG_KERNEL_STACK_OVERFLOW_CHECK=y
+CONFIG_KERNEL_BANNER=y
+# CONFIG_KERNEL_HOOK is not set
+# CONFIG_KERNEL_SOFTTIMER=y
+# CONFIG_KERNEL_IDLE_HOOK=y
+# CONFIG_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_KTASK_STACKSIZE=512
+CONFIG_ZOMBIE_KTASK_STACKSIZE=512
+# CONFIG_KERNEL_TASK_ISOLATION is not set
+
+#
+# Memory Management
+#
+# CONFIG_KERNEL_MEMBLOCK is not set
+
+#
+# Command shell
+#
+CONFIG_TOOL_SHELL=y
+CONFIG_SHELL_TASK_PRIORITY=4
+CONFIG_SHELL_TASK_STACK_SIZE=2048
+
+#
+# User Control
+#
+CONFIG_SHELL_DEFAULT_USER="letter"
+CONFIG_SHELL_DEFAULT_USER_PASSWORD=""
+CONFIG_SHELL_LOCK_TIMEOUT=10000
+CONFIG_SHELL_ENTER_CR_AND_LF=y
+# CONFIG_SHELL_ENTER_CRLF is not set
+CONFIG_SHELL_ENTER_CR=y
+CONFIG_SHELL_ENTER_LF=y
+CONFIG_SHELL_MAX_NUMBER=5
+CONFIG_SHELL_PARAMETER_MAX_NUMBER=8
+CONFIG_SHELL_HISTORY_MAX_NUMBER=5
+CONFIG_SHELL_PRINT_BUFFER=128
+CONFIG_SHELL_USING_CMD_EXPORT=y
+# CONFIG_SHELL_HELP_LIST_USER is not set
+CONFIG_SHELL_HELP_SHOW_PERMISSION=y
+# CONFIG_SHELL_HELP_LIST_VAR is not set
+# CONFIG_SHELL_HELP_LIST_KEY is not set
+#CONFIG_KERNEL_QUEUEMANAGE=y
+# CONFIG_KERNEL_WORKQUEUE is not set
+CONFIG_WORKQUEUE_KTASK_STACKSIZE=256
+CONFIG_WORKQUEUE_KTASK_PRIORITY=2
+CONFIG_QUEUE_MAX=2
+CONFIG_KERNEL_WAITQUEUE=y
+CONFIG_KERNEL_DATAQUEUE=y
+# CONFIG_KERNEL_CIRCULAR_AREA is not set
+# CONFIG_KERNEL_AVL_TREE is not set
+CONFIG_NAME_MAX=32
+CONFIG_ALIGN_SIZE=8
+CONFIG_KERNEL_COMPONENTS_INIT=n
+CONFIG_KERNEL_USER_MAIN=y
+CONFIG_MAIN_KTASK_STACK_SIZE=2048
+CONFIG_ENV_INIT_KTASK_STACK_SIZE=2048
+CONFIG_MAIN_KTASK_PRIORITY=3
+# CONFIG_USER_TEST is not set
+# CONFIG_TOOL_TEST_SEM is not set
+# CONFIG_TOOL_TEST_MUTEX is not set
+# CONFIG_TOOL_TEST_EVENT is not set
+# CONFIG_TOOL_TEST_MSG is not set
+# CONFIG_TOOL_TEST_AVLTREE is not set
+# CONFIG_TEST_CRICULAR_AREA is not set
+# CONFIG_TOOL_TEST_MEM is not set
+# CONFIG_TOOL_TEST_TIMER is not set
+# CONFIG_TOOL_TEST_IWG is not set
+# CONFIG_TOOL_TEST_REALTIME is not set
+# CONFIG_TOOL_TEST_DBG is not set
+# CONFIG_TOOL_TEST_SCHED is not set
+# CONFIG_KERNEL_DEBUG is not set
+#CONFIG_DEBUG_INIT_CONFIG=y
+#CONFIG_DBG_INIT=1
+#CONFIG_ARCH_SMP=y
+#CONFIG_CPUS_NR=2
+
+#
+# hash table config
+#
+CONFIG_ID_HTABLE_SIZE=4
+CONFIG_ID_NUM_MAX=16
+
+#
+# File system
+#
+CONFIG_FS_DFS=n
+#CONFIG_DFS_USING_WORKDIR=y
+#CONFIG_FS_DFS_DEVFS=y
+
+#
+# Fat filesystem 
+#
+
+#
+# IOT-Device File system
+#
+
+#
+# Lwext4 filesystem 
+#
+
+#
+# APP Framework
+#
+
+#
+# Perception
+#
+# CONFIG_PERCEPTION_SENSORDEVICE is not set
+
+#
+# connection
+#
+# CONFIG_CONNECTION_AT is not set
+# CONFIG_CONNECTION_MQTT is not set
+
+#
+# medium communication 
+#
+
+
+#
+# Intelligence
+#
+
+#
+# Control
+#
+
+#
+# Lib
+#
+CONFIG_LIB=y
+CONFIG_LIB_POSIX=y
+CONFIG_LIB_NEWLIB=y
+
+# CONFIG_LITTLEVGL2RTT_USING_DEMO=y
+
+#
+# Security
+#

board/cortex-m3-emulator/Kconfig

@@ -0,0 +1,56 @@
+mainmenu "XiUOS Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config KERNEL_DIR
+    string
+    option env="KERNEL_ROOT"
+    default "../.."
+
+config BOARD_CORTEX_M3_EVB
+    bool
+    select  ARCH_ARM
+    default y
+
+config KERNEL_CONSOLE_DEVICE_NAME
+    string
+    default "uart0"
+
+
+source "$KERNEL_DIR/arch/Kconfig"
+
+menu "cortex-m3 emulator feature"
+    source "$BSP_DIR/third_party_driver/Kconfig"
+
+    menu "config default board resources"
+        menu "config board app name"
+            config BOARD_APP_NAME
+                string "config board app name"
+                default "/XiUOS_cortex-m3-emulator_app.bin"
+        endmenu
+
+        menu "config board service table"
+            config SERVICE_TABLE_ADDRESS
+                hex "board service table address"
+                default 0x2007F0000
+        endmenu
+
+    endmenu
+
+    config __STACKSIZE__
+        int "stack size for interrupt"
+        default 4096
+
+endmenu
+
+
+menu "Hardware feature"
+source "$KERNEL_DIR/resources/Kconfig"
+endmenu
+
+source "$KERNEL_DIR/Kconfig"
+
+

board/cortex-m3-emulator/Makefile

@@ -0,0 +1,5 @@
+SRC_DIR := third_party_driver 
+
+SRC_FILES := board.c connect_uart.c
+
+include $(KERNEL_ROOT)/compiler.mk

board/cortex-m3-emulator/README.md

@@ -0,0 +1,187 @@
+# 从零开始构建矽璓工业物联操作系统：使用ARM架构的cortex-m3 emulator
+
+# cortex-m3 emulator
+
+[XiUOS](http://xuos.io/) (X Industrial Ubiquitous Operating System) 矽璓XiUOS是一款面向智慧车间的工业物联网操作系统，主要由一个极简的微型实时操作系统内核和其上的工业物联框架构成，通过高效管理工业物联网设备、支撑工业物联应用，在生产车间内实现智能化的“感知环境、联网传输、知悉识别、控制调整”，促进以工业设备和工业控制系统为核心的人、机、物深度互联，帮助提升生产线的数字化和智能化水平。
+
+## 1. 简介
+
+Q‎EMU 是一个通用的开源模拟器和虚拟化工具。目前Q‎EMU已经可以较完整的支持ARM cortex-m3架构。XiUOS同样支持运行在Q‎EMU上
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| lm3s6965evb |
+|架构| cortex-m3 |
+|主频| 50MHz |
+|片内SRAM| 64KB |
+| 外设支持 | UART |
+
+XiUOS板级当前支持使用UART。
+
+## 2. 开发环境搭建
+
+### 推荐使用：
+
+**操作系统：** ubuntu18.04 [https://ubuntu.com/download/desktop](https://ubuntu.com/download/desktop)
+
+更新`ubuntu 18.04`源的方法:（根据自身情况而定，可以不更改）
+
+第一步:打开sources.list文件
+
+```c
+sudo vim /etc/apt/sources.list
+```
+
+第二步:将以下内容复制到sources.list文件
+
+```c
+deb http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
+deb http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-security main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-updates main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-proposed main restricted universe multiverse
+deb-src http://mirrors.aliyun.com/ubuntu/ bionic-backports main restricted universe multiverse
+```
+
+第三步:更新源和系统软件
+
+```c
+sudo apt-get update
+sudo apt-get upgrade
+```
+
+**开发工具推荐使用 VSCode   ，VScode下载地址为：** VSCode  [https://code.visualstudio.com/](https://code.visualstudio.com/)，推荐下载地址为 [http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb](http://vscode.cdn.azure.cn/stable/3c4e3df9e89829dce27b7b5c24508306b151f30d/code_1.55.2-1618307277_amd64.deb)
+
+### 依赖包安装：
+
+```
+$ sudo apt install build-essential pkg-config  git
+$ sudo apt install gcc make libncurses5-dev openssl libssl-dev bison flex libelf-dev autoconf libtool gperf libc6-dev
+```
+
+**XiUOS操作系统源码下载：** XiUOS [https://forgeplus.trustie.net/projects/xuos/xiuos](https://forgeplus.trustie.net/projects/xuos/xiuos)
+
+新建一个空文件夹并进入文件夹中，并下载源码，具体命令如下：
+
+```c
+mkdir test  &&  cd test
+git clone https://git.trustie.net/xuos/xiuos.git
+```
+
+打开源码文件包可以看到以下目录：
+| 名称 | 说明 |
+| -- | -- |
+| application | 应用代码 |
+| board | 板级支持包 |
+| framework | 应用框架 |
+| fs | 文件系统 |
+| kernel | 内核源码 |
+| resources | 驱动文件 |
+| tool | 系统工具 |
+
+使用VScode打开代码，具体操作步骤为：在源码文件夹下打开系统终端，输入`code .`即可打开VScode开发环境，如下图所示：
+
+<div align= "center"> 
+<img src = img/vscode.jpg  width =1000>
+  </div>
+
+### 裁减配置工具的下载
+
+裁减配置工具：
+
+**工具地址：** kconfig-frontends [https://forgeplus.trustie.net/projects/xuos/kconfig-frontends](https://forgeplus.trustie.net/projects/xuos/kconfig-frontends)，下载与安装的具体命令如下：
+
+```c
+mkdir kfrontends  && cd kfrontends
+git  clone https://git.trustie.net/xuos/kconfig-frontends.git
+```
+
+下载源码后按以下步骤执行软件安装：
+
+```c
+cd kconfig-frontends
+ ./xs_build.sh
+```
+
+### 编译工具链：
+
+ARM： arm-none-eabi(`gcc version 6.3.1`)，默认安装到Ubuntu的/usr/bin/arm-none-eabi-，使用如下命令行下载和安装。
+
+```shell
+$ sudo apt install gcc-arm-none-eabi
+```
+
+## 编译说明
+
+### 编辑环境：`Ubuntu18.04`
+
+### 编译工具链：`arm-none-eabi-gcc`
+使用`VScode`打开工程的方法有多种，本文介绍一种快捷键，在项目目录下将`code .`输入linux系统命令终端即可打开目标项目
+
+
+编译步骤：
+
+1.在VScode命令终端中执行以下命令，生成配置文件
+
+```c
+   make BOARD=cortex-m3-emulator menuconfig
+```
+
+2.在menuconfig界面配置需要关闭和开启的功能，按回车键进入下级菜单，按Y键选中需要开启的功能，按N键选中需要关闭的功能，配置结束后保存并退出（本例旨在演示简单的输出例程，所以没有需要配置的选项，双击快捷键ESC退出配置）
+
+![menuconfig](img/menuconfig.png)
+
+退出时选择`yes`保存上面所配置的内容，如下图所示：
+
+![menuconfig1](img/menuconfig1.png)
+
+3.继续执行以下命令，进行编译
+
+```
+make BOARD=cortex-m3-emulator
+```
+
+4.如果编译正确无误，会产生XiUOS_cortex-m3-emulator.elf、XiUOS_cortex-m3-emulator.bin文件。
+
+## 3. 运行
+
+### 3.1 安装Q‎EMU
+
+```
+sudo apt install qemu-system-arm
+```
+
+### 3.2 运行结果
+
+通过以下命令启动Q‎EMU并加载XiUOS ELF文件
+
+```
+qemu-system-arm -machine  lm3s6965evb -nographic -kernel build/XiUOS_cortex-m3-emulator.elf
+```
+
+QEMU运行起来后将会在终端上看到信息打印输出
+
+![terminal](img/terminal.png)
+
+### 3.3 调试
+
+通过Q‎EMU可以方便的对XiUOS进行调试，首先安装gdb调试工具
+```
+sudo apt install gdb-multiarch
+```
+
+并通过以下命令启动Q‎EMU
+
+```
+qemu-system-arm -machine  lm3s6965evb -nographic -kernel build/XiUOS_cortex-m3-emulator.elf -s -S
+```
+
+然后要重新开启另一个linux系统终端一个终端，执行`riscv-none-embed-gdb`命令
+
+```
+gdb-multiarch build/XiUOS_cortex-m3-emulator.elf -ex "target remote localhost:1234" 
+```

board/cortex-m3-emulator/board.c

@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.c
+* @brief support cortex-m3-emulator init configure and start-up
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-13
+*/
+
+
+#include <board.h>
+#include <xiuos.h>
+#include <device.h>
+#include <arch_interrupt.h>
+
+void SysTick_Handler(int irqn, void *arg)
+{
+    TickAndTaskTimesliceUpdate();
+}
+DECLARE_HW_IRQ(SYSTICK_IRQN, SysTick_Handler, NONE);
+
+void InitBoardHardware()
+{
+	extern int InitHwUart(void);
+	InitHwUart();
+	InstallConsole(SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1, SERIAL_DEVICE_NAME_1);
+	InitBoardMemory((void*)LM3S_SRAM_START, (void*)LM3S_SRAM_END);
+
+}

board/cortex-m3-emulator/board.h

@@ -0,0 +1,38 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file board.h
+* @brief define cortex-m3-emulator init configure and start-up function
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-13
+*/
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+
+extern  void *__bss_end;
+extern  void *_heap_end;
+#define MEM_OFFSET  0x20002000 
+#define LM3S_SRAM_START         ( ( ((unsigned long)(&__bss_end)) > MEM_OFFSET)? (unsigned long)(&__bss_end):(MEM_OFFSET)  )
+#define LM3S_SRAM_END          ( &_heap_end )
+
+#define BSP_USING_UART1
+#define SERIAL_BUS_NAME_1 "uart0"
+#define SERIAL_DRV_NAME_1 "uart0_drv"
+#define SERIAL_DEVICE_NAME_1 "uart0_dev0"
+
+
+
+#endif

board/cortex-m3-emulator/config.mk

@@ -0,0 +1,14 @@
+export CROSS_COMPILE ?=/usr/bin/arm-none-eabi-
+
+export CFLAGS := -mcpu=cortex-m3 -mthumb  -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g -fgnu89-inline -Wa,-mimplicit-it=thumb 
+export AFLAGS := -c -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb  -gdwarf-2
+export LFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_cortex-m3-emulator.map,-cref,-u,Reset_Handler -T $(BSP_ROOT)/link.lds
+export CXXFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Dgcc -O0 -gdwarf-2 -g 
+
+export APPLFLAGS := -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=XiUOS_app.map,-cref,-u, -T $(BSP_ROOT)/link_userspace.lds
+
+
+export DEFINES := -DHAVE_CCONFIG_H  
+
+export ARCH = arm
+export MCU = cortex-m3

board/cortex-m3-emulator/connect_uart.c

@@ -0,0 +1,351 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+/**
+* @file connect_uart.c
+* @brief support cortex_m3_emulator board uart function and register to bus framework
+* @version 1.0 
+* @author AIIT XUOS Lab
+* @date 2021-05-10
+*/
+
+#include <board.h>
+#include <xiuos.h>
+#include <device.h>
+#include <inc/hw_types.h>
+#include <driverlib/gpio.h>
+#include <driverlib/interrupt.h>
+#include <driverlib/sysctl.h>
+#include <driverlib/uart.h>
+#include <inc/hw_ints.h>
+#include <inc/hw_memmap.h>
+#include <inc/hw_uart.h>
+
+#ifdef BSP_USING_UART1
+static struct SerialBus serial_bus_1;
+static struct SerialDriver serial_driver_1;
+static struct SerialHardwareDevice serial_device_1;
+#endif
+#ifdef BSP_USING_UART2
+static struct SerialBus serial_bus_2;
+static struct SerialDriver serial_driver_2;
+static struct SerialHardwareDevice serial_device_2;
+#endif
+
+static void SerialCfgParamCheck(struct SerialCfgParam *serial_cfg_default, struct SerialCfgParam *serial_cfg_new)
+{
+    struct SerialDataCfg *data_cfg_default = &serial_cfg_default->data_cfg;
+    struct SerialDataCfg *data_cfg_new = &serial_cfg_new->data_cfg;
+
+    if ((data_cfg_default->serial_baud_rate != data_cfg_new->serial_baud_rate) && (data_cfg_new->serial_baud_rate)) {
+        data_cfg_default->serial_baud_rate = data_cfg_new->serial_baud_rate;
+    }
+
+    if ((data_cfg_default->serial_bit_order != data_cfg_new->serial_bit_order) && (data_cfg_new->serial_bit_order)) {
+        data_cfg_default->serial_bit_order = data_cfg_new->serial_bit_order;
+    }
+
+    if ((data_cfg_default->serial_buffer_size != data_cfg_new->serial_buffer_size) && (data_cfg_new->serial_buffer_size)) {
+        data_cfg_default->serial_buffer_size = data_cfg_new->serial_buffer_size;
+    }
+
+    if ((data_cfg_default->serial_data_bits != data_cfg_new->serial_data_bits) && (data_cfg_new->serial_data_bits)) {
+        data_cfg_default->serial_data_bits = data_cfg_new->serial_data_bits;
+    }
+
+    if ((data_cfg_default->serial_invert_mode != data_cfg_new->serial_invert_mode) && (data_cfg_new->serial_invert_mode)) {
+        data_cfg_default->serial_invert_mode = data_cfg_new->serial_invert_mode;
+    }
+
+    if ((data_cfg_default->serial_parity_mode != data_cfg_new->serial_parity_mode) && (data_cfg_new->serial_parity_mode)) {
+        data_cfg_default->serial_parity_mode = data_cfg_new->serial_parity_mode;
+    }
+
+    if ((data_cfg_default->serial_stop_bits != data_cfg_new->serial_stop_bits) && (data_cfg_new->serial_stop_bits)) {
+        data_cfg_default->serial_stop_bits = data_cfg_new->serial_stop_bits;
+    }
+}
+
+static void UartHandler(struct SerialBus *serial_bus, struct SerialDriver *serial_drv)
+{
+    struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)serial_bus->bus.owner_haldev;
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; 
+
+    uint32 status;
+
+    status = UARTIntStatus(serial_cfg->hw_cfg.serial_register_base, RET_TRUE);
+
+    /* clear interrupt status */
+    UARTIntClear(serial_cfg->hw_cfg.serial_register_base, status);
+
+    while (UARTCharsAvail(serial_cfg->hw_cfg.serial_register_base)) {
+        SerialSetIsr(serial_dev, SERIAL_EVENT_RX_IND);
+    }
+}
+
+#ifdef BSP_USING_UART1
+void UartIsr1(int vector, void *param)
+{
+	/* get serial bus 1 */
+	UartHandler(&serial_bus_1, &serial_driver_1);
+}
+DECLARE_HW_IRQ(UART1_IRQn, UartIsr1, NONE);
+#endif
+
+#ifdef BSP_USING_UART2
+void UartIsr2(int irqno)
+{
+	/* get serial bus 2 */
+	UartHandler(&serial_bus_2, &serial_driver_2);
+}
+#endif
+
+static uint32 SerialInit(struct SerialDriver *serial_drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(serial_drv);
+
+    return EOK;
+}
+
+static uint32 SerialConfigure(struct SerialDriver *serial_drv, int serial_operation_cmd)
+{
+    NULL_PARAM_CHECK(serial_drv);
+
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_drv->private_data; 
+    struct HardwareDev *dev = serial_drv->driver.owner_bus->owner_haldev;
+    struct SerialHardwareDevice *serial_dev = (struct SerialHardwareDevice *)dev;
+    struct SerialDevParam *serial_dev_param = (struct SerialDevParam *)serial_dev->haldev.private_data;
+
+    if (OPER_CLR_INT == serial_operation_cmd) {
+        if (SIGN_OPER_INT_RX & serial_dev_param->serial_work_mode) {
+            /* disable UART rx interrupt */
+            UARTIntDisable(serial_cfg->hw_cfg.serial_register_base, UART_INT_RX | UART_INT_RT);
+        }
+	} else if (OPER_SET_INT == serial_operation_cmd) {
+        /* enable interrupt */
+        if (UART0_BASE == serial_cfg->hw_cfg.serial_register_base)
+            IntEnable(INT_UART0);
+        else if (UART1_BASE == serial_cfg->hw_cfg.serial_register_base)
+            IntEnable(INT_UART1);
+
+        UARTIntEnable(serial_cfg->hw_cfg.serial_register_base, UART_INT_RX | UART_INT_RT);
+    }
+
+    return EOK;
+}
+
+static uint32 SerialDrvConfigure(void *drv, struct BusConfigureInfo *configure_info)
+{
+    NULL_PARAM_CHECK(drv);
+    NULL_PARAM_CHECK(configure_info);
+
+    x_err_t ret = EOK;
+    int serial_operation_cmd;
+    struct SerialDriver *serial_drv = (struct SerialDriver *)drv;
+
+    switch (configure_info->configure_cmd)
+    {
+        case OPE_INT:
+            ret = SerialInit(serial_drv, configure_info);
+            break;
+        case OPE_CFG:
+            serial_operation_cmd = *(int *)configure_info->private_data;
+            ret = SerialConfigure(serial_drv, serial_operation_cmd);
+            break;
+        default:
+            break;
+    }
+
+    return ret;
+}
+
+static int SerialPutChar(struct SerialHardwareDevice *serial_dev, char c)
+{
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data;
+    while (UARTCharPutNonBlocking(serial_cfg->hw_cfg.serial_register_base, c) == RET_FALSE);
+
+    return 0;
+}
+
+static int SerialGetChar(struct SerialHardwareDevice *serial_dev)
+{
+    struct SerialCfgParam *serial_cfg = (struct SerialCfgParam *)serial_dev->private_data; 
+    long val = UARTCharGetNonBlocking(serial_cfg->hw_cfg.serial_register_base);
+    if (val > 0)
+        return (int)val;
+    else
+        return -1;
+}
+
+static const struct SerialDataCfg data_cfg_init = 
+{
+    .serial_baud_rate = BAUD_RATE_115200,
+    .serial_data_bits = DATA_BITS_8,
+    .serial_stop_bits = STOP_BITS_1,
+    .serial_parity_mode = PARITY_NONE,
+    .serial_bit_order = BIT_ORDER_LSB,
+    .serial_invert_mode = NRZ_NORMAL,
+    .serial_buffer_size = SERIAL_RB_BUFSZ,
+};
+
+/*manage the serial device operations*/
+static const struct SerialDrvDone drv_done =
+{
+    .init = SerialInit,
+    .configure = SerialConfigure,
+};
+
+/*manage the serial device hal operations*/
+static struct SerialHwDevDone hwdev_done =
+{
+    .put_char = SerialPutChar,
+    .get_char = SerialGetChar,
+};
+
+static int BoardSerialBusInit(struct SerialBus *serial_bus, struct SerialDriver *serial_driver, const char *bus_name, const char *drv_name)
+{
+    x_err_t ret = EOK;
+
+    /*Init the serial bus */
+    ret = SerialBusInit(serial_bus, bus_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialBusInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Init the serial driver*/
+    ret = SerialDriverInit(serial_driver, drv_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialDriverInit error %d\n", ret);
+        return ERROR;
+    }
+
+    /*Attach the serial driver to the serial bus*/
+    ret = SerialDriverAttachToBus(drv_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialDriverAttachToBus error %d\n", ret);
+        return ERROR;
+    } 
+
+    return ret;
+}
+
+/*Attach the serial device to the serial bus*/
+static int BoardSerialDevBend(struct SerialHardwareDevice *serial_device, void *serial_param, const char *bus_name, const char *dev_name)
+{
+    x_err_t ret = EOK;
+
+    ret = SerialDeviceRegister(serial_device, serial_param, dev_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialDeviceInit device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }  
+
+    ret = SerialDeviceAttachToBus(dev_name, bus_name);
+    if (EOK != ret) {
+        KPrintf("InitHwUart SerialDeviceAttachToBus device %s error %d\n", dev_name, ret);
+        return ERROR;
+    }  
+
+    return  ret;
+}
+
+int InitHwUart(void)
+{
+    x_err_t ret = EOK;
+
+#ifdef BSP_USING_UART1
+    memset(&serial_bus_1, 0, sizeof(struct SerialBus));
+    memset(&serial_driver_1, 0, sizeof(struct SerialDriver));
+    memset(&serial_device_1, 0, sizeof(struct SerialHardwareDevice));
+
+    static struct SerialCfgParam serial_cfg_1;
+    memset(&serial_cfg_1, 0, sizeof(struct SerialCfgParam));
+
+    static struct SerialDevParam serial_dev_param_1;
+    memset(&serial_dev_param_1, 0, sizeof(struct SerialDevParam));
+    
+    serial_driver_1.drv_done = &drv_done;
+    serial_driver_1.configure = &SerialDrvConfigure;
+    serial_device_1.hwdev_done = &hwdev_done;
+
+    serial_cfg_1.data_cfg = data_cfg_init;
+
+    serial_cfg_1.hw_cfg.serial_register_base   = UART0_BASE;
+    serial_driver_1.private_data = (void *)&serial_cfg_1;
+
+    serial_dev_param_1.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_1.haldev.private_data = (void *)&serial_dev_param_1;
+
+	/* enable UART0 clock */
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
+
+	/* set UART0 pinmux */
+    GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
+
+	/* Configure the UART for 115,200, 8-N-1 operation. */
+	UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), serial_cfg_1.data_cfg.serial_baud_rate,
+                        (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
+                         UART_CONFIG_PAR_NONE));
+
+    ret = BoardSerialBusInit(&serial_bus_1, &serial_driver_1, SERIAL_BUS_NAME_1, SERIAL_DRV_NAME_1);
+    if (EOK != ret) {
+        KPrintf("InitHwUart uarths error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_1, (void *)&serial_cfg_1, SERIAL_BUS_NAME_1, SERIAL_DEVICE_NAME_1);
+    if (EOK != ret) {
+        KPrintf("InitHwUart uarths error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+#ifdef BSP_USING_UART2
+    memset(&serial_bus_2, 0, sizeof(struct SerialBus));
+    memset(&serial_driver_2, 0, sizeof(struct SerialDriver));
+    memset(&serial_device_2, 0, sizeof(struct SerialHardwareDevice));
+
+    static struct SerialCfgParam serial_cfg_2;
+    memset(&serial_cfg_2, 0, sizeof(struct SerialCfgParam));
+
+    static struct SerialDevParam serial_dev_param_2;
+    memset(&serial_dev_param_2, 0, sizeof(struct SerialDevParam));
+    
+    serial_driver_2.drv_done = &drv_done;
+    serial_driver_2.configure = &SerialDrvConfigure;
+    serial_device_2.hwdev_done = &hwdev_done;
+
+    serial_cfg_2.data_cfg = data_cfg_init;
+
+    serial_cfg_2.hw_cfg.serial_register_base   = UART1_BASE;
+    serial_driver_2.private_data = (void *)&serial_cfg_2;
+
+    serial_dev_param_2.serial_work_mode = SIGN_OPER_INT_RX;
+    serial_device_2.haldev.private_data = (void *)&serial_dev_param_2;
+
+    ret = BoardSerialBusInit(&serial_bus_2, &serial_driver_2, SERIAL_BUS_NAME_2, SERIAL_DRV_NAME_2);
+    if (EOK != ret) {
+        KPrintf("InitHwUart uarths error ret %u\n", ret);
+        return ERROR;
+    }
+
+    ret = BoardSerialDevBend(&serial_device_2, (void *)&serial_cfg_2, SERIAL_BUS_NAME_2, SERIAL_DEVICE_NAME_2);
+    if (EOK != ret) {
+        KPrintf("InitHwUart uarths error ret %u\n", ret);
+        return ERROR;
+    }    
+#endif
+
+    return ret;
+}

board/cortex-m3-emulator/link.lds

@@ -0,0 +1,97 @@
+/*
+* Copyright (c) 2020 AIIT XUOS Lab
+* XiUOS is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2.
+* You may obtain a copy of Mulan PSL v2 at:
+*        http://license.coscl.org.cn/MulanPSL2
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+* See the Mulan PSL v2 for more details.
+*/
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+OUTPUT_ARCH(arm)
+
+__SYSTEM_STACKSIZE__ = 0x1000;
+
+ENTRY(Reset_Handler)
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text .text.*)               
+        *(.rodata .rodata*)             /* read-only data (constants) */
+        *(.glue_7)
+        *(.glue_7t)
+
+        /* section information for  shell */
+        . = ALIGN(4);
+        _shell_command_start = .;
+        KEEP (*(shellCommand))
+        _shell_command_end = .;
+        . = ALIGN(4);
+      
+        __isrtbl_idx_start = .;
+        KEEP(*(.isrtbl.idx))
+        __isrtbl_start = .;
+        KEEP(*(.isrtbl))
+        __isrtbl_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(g_service_table_start = ABSOLUTE(.));
+        KEEP(*(.g_service_table))
+        PROVIDE(g_service_table_end = ABSOLUTE(.));
+
+        PROVIDE(_etext =  ABSOLUTE(.));
+
+        _etext = .;
+    } > flash = 0
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        _sidata = .;
+    } > flash
+    __exidx_end = .;
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        . = ALIGN(4);
+        _edata = . ;
+    } >sram
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        _sbss = .;
+        *(.bss)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+    } > sram
+    __bss_end = .;
+    _end = .;
+
+   .stack ORIGIN(sram) + LENGTH(sram) - __SYSTEM_STACKSIZE__ :
+  {
+    PROVIDE( _heap_end = . );
+    . = __SYSTEM_STACKSIZE__;
+    PROVIDE( _sp = . );
+  } >sram 
+   
+}

board/cortex-m3-emulator/third_party_driver/Libraries/Makefile

@@ -0,0 +1,3 @@
+SRC_DIR := driverlib
+
+include $(KERNEL_ROOT)/compiler.mk

board/cortex-m3-emulator/third_party_driver/Libraries/driverlib/Makefile

@@ -0,0 +1,3 @@
+SRC_FILES := gpio.c interrupt.c sysctl.c uart.c
+
+include $(KERNEL_ROOT)/compiler.mk

board/cortex-m3-emulator/third_party_driver/Libraries/driverlib/cpu.h

@@ -0,0 +1,75 @@
+//*****************************************************************************
+//
+// cpu.h - Prototypes for the CPU instruction wrapper functions.
+//
+// Copyright (c) 2006-2013 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 10636 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern unsigned long CPUcpsid(void);
+extern unsigned long CPUcpsie(void);
+extern unsigned long CPUprimask(void);
+extern void CPUwfi(void);
+extern unsigned long CPUbasepriGet(void);
+extern void CPUbasepriSet(unsigned long ulNewBasepri);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif